公开(公告)号：US6046642A

公开(公告)日：2000-04-04

申请号：US149520

申请日：1998-09-08

申请人： Daniel C. Brayton ,  Jeffrey K. Jones ,  Robert S. Kaltenecker ,  Bill Tabano Agar, Jr.

发明人： Daniel C. Brayton ,  Jeffrey K. Jones ,  Robert S. Kaltenecker ,  Bill Tabano Agar, Jr.

IPC分类号： H03F1/30 ,  H03F3/193 ,  H03F3/45 ,  H03G1/30

CPC分类号： H03F3/193 ,  H03F1/301 ,  H03F3/45089 ,  H03F3/45475 ,  H03F3/45538 ,  H03F2203/45392 ,  H03F2203/45498 ,  H03F2203/45542 ,  H03F2203/45638

摘要： An active bias compensation circuit (110) senses a quiescent current flowing in an amplifier (130) and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier (130) over a wide range of factors, e.g., temperature variation, process variation, history of the amplifier (130), etc. The compensation circuit (110) includes two transistors (101, 102) forming a difference amplifier. A sensing voltage proportional to the quiescent current and a reference voltage are applied to the base electrodes of the two transistors (101, 102), which generates a bias signal in response to a difference between the sensing voltage and the reference voltage. The bias signal adjusts the quiescent current in the amplifier (130).

摘要翻译： 有源偏置补偿电路（110）感测在放大器（130）中流动的静态电流并且调整静态电流以在宽范围的因素（例如，温度变化，过程变化）上维持放大器（130）的最佳DC偏置 ，放大器（130）的历史等。补偿电路（110）包括形成差分放大器的两个晶体管（101,102）。 与静态电流成比例的感测电压和参考电压施加到两个晶体管（101,102）的基极，其响应于感测电压和参考电压之间的差产生偏置信号。 偏置信号调节放大器（130）中的静态电流。

公开(公告)号：US20150381121A1

公开(公告)日：2015-12-31

申请号：US14317572

申请日：2014-06-27

申请人： Jeffrey K. Jones ,  Basim H. Noori ,  Michael E. Watts

发明人： Jeffrey K. Jones ,  Basim H. Noori ,  Michael E. Watts

IPC分类号： H03F3/19 ,  H01L25/16 ,  H01L49/02 ,  H03F3/21 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00 ,  H03F1/56 ,  H01L25/00 ,  H01L21/56

CPC分类号： H03F3/21 ,  H01G4/385 ,  H01G4/40 ,  H01L23/047 ,  H01L23/481 ,  H01L23/488 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/19104 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： An embodiment of an integrated passive device (IPD) assembly includes a first capacitor formed over a semiconductor substrate, where the first capacitor includes a first capacitor electrode, a second capacitor electrode, and dielectric material that electrically insulates the first capacitor electrode from the second capacitor electrode. The IPD assembly also includes a first contact pad exposed at a top surface of the IPD assembly and electrically coupled to the second capacitor electrode, and a second contact pad exposed at the top surface of the IPD. A second capacitor is coupled to the top surface of the IPD, and includes a first terminal electrically coupled to the first contact pad, and a second terminal electrically coupled to the second contact pad. The IPD assembly may be included in a packaged RF device, forming portions of an output impedance matching circuit and an envelope frequency termination circuit.

摘要翻译： 集成无源器件（IPD）组件的实施例包括形成在半导体衬底上的第一电容器，其中第一电容器包括第一电容器电极，第二电容器电极和将第一电容器电极与第二电容器电绝缘的电介质材料 电极。 IPD组件还包括暴露在IPD组件的顶表面处并电耦合到第二电容器电极的第一接触焊盘和暴露在IPD的顶表面处的第二接触焊盘。 第二电容器耦合到IPD的顶表面，并且包括电耦合到第一接触焊盘的第一端子和电耦合到第二接触焊盘的第二端子。 IPD组件可以包括在封装的RF器件中，形成输出阻抗匹配电路的一部分和封装频率终止电路。

公开(公告)号：US08134241B2

公开(公告)日：2012-03-13

申请号：US13179295

申请日：2011-07-08

申请人： Jeffrey K. Jones ,  Margaret A. Szymanowski ,  Michele L. Miera ,  Xiaowei Ren ,  Wayne R. Burger ,  Mark A. Bennett ,  Colin Kerr

发明人： Jeffrey K. Jones ,  Margaret A. Szymanowski ,  Michele L. Miera ,  Xiaowei Ren ,  Wayne R. Burger ,  Mark A. Bennett ,  Colin Kerr

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L29/0649 ,  H01L2224/05076 ,  H01L2224/05558 ,  H01L2224/05576 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

摘要翻译： 在共同衬底上具有有源器件区域和焊盘（BP）区域的电子元件期望地包括位于BP之下的电介质区域，以在电子元件被缩放到更高功率和/或操作时降低BP的寄生阻抗及其互连 频率。 由平原（例如，仅氧化物）电介质区域产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有比它们被嵌入和/或更靠近衬底TEC的介电材料的热膨胀系数小的热膨胀系数（TEC）的电隔离夹杂物的复合电介质区域来避免。 对于硅衬底，聚硅或非晶硅适用于介电材料的夹杂物和氧化硅。 夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。

公开(公告)号：US07378920B2

公开(公告)日：2008-05-27

申请号：US11354472

申请日：2006-02-14

申请人： Jeffrey K. Jones ,  Basim H. Noori

发明人： Jeffrey K. Jones ,  Basim H. Noori

IPC分类号： H03H7/38

CPC分类号： H03H7/38 ,  H01L2223/6655 ,  H03F1/565 ,  H03F3/191 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/402 ,  H03F2200/451

摘要： An output match circuit is coupled between the terminal of a high-frequency device and a ground terminal. The output match circuit includes an LC shunt and an LC notch serially coupled to the LC shunt, wherein the LC notch includes a resonant capacitive element in series with a resonant inductive element. The LC notch may simply include a resonant inductive element coupled directly to the ground terminal. The series inductive element may have a terminal coupled between the resonant capacitive element and the resonant inductive element.

摘要翻译： 输出匹配电路耦合在高频器件的端子和接地端子之间。 输出匹配电路包括串联耦合到LC分流器的LC分路和LC陷波，其中LC陷波包括与谐振电感元件串联的谐振电容元件。 LC陷波可以简单地包括直接耦合到接地端子的谐振电感元件。 串联电感元件可以具有耦合在谐振电容元件和谐振电感元件之间的端子。

公开(公告)号：US09401682B2

公开(公告)日：2016-07-26

申请号：US14489868

申请日：2014-09-18

申请人： Igor Ivanovich Blednov ,  Jeffrey K. Jones ,  Youri Volokhine

发明人： Igor Ivanovich Blednov ,  Jeffrey K. Jones ,  Youri Volokhine

IPC分类号： H01L23/10 ,  H03F3/195 ,  H03F3/213 ,  H01L23/66 ,  H03F1/08 ,  H03F1/30 ,  H03F3/24

CPC分类号： H03F3/195 ,  H01L23/66 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/19107 ,  H03F1/086 ,  H03F1/301 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/447 ,  H03F2200/451 ,  H01L2924/00014

摘要： A RF power amplifier module comprises a die with a RF power transistor and the RF power transistor comprises a control terminal, a transistor output terminal and a transistor reference terminal. The RF power amplifier module further comprises a module input terminal, a module output terminal and at least two module reference terminals being electrically coupled to the control terminal, the transistor output terminal and the transistor reference terminal, respectively. The RF power amplifier module further comprises an electrically isolating layer and a heat conducting element. The die is in thermal contact with the heat conducting element via the electrically isolating layer in order to transfer heat during operation of the RF power transistor to the heat conducting element.

摘要翻译： RF功率放大器模块包括具有RF功率晶体管的管芯，RF功率晶体管包括控制端子，晶体管输出端子和晶体管参考端子。 RF功率放大器模块还包括模块输入端子，模块输出端子和至少两个模块参考端子，其分别电耦合到控制端子，晶体管输出端子和晶体管参考端子。 RF功率放大器模块还包括电绝缘层和导热元件。 模具通过电绝缘层与导热元件热接触，以便在RF功率晶体管的操作期间将热量传递到导热元件。

公开(公告)号：US20100140814A1

公开(公告)日：2010-06-10

申请号：US12328319

申请日：2008-12-04

申请人： Jeffrey K. Jones ,  Margaret A. Szymanowski ,  Michele L. Miera ,  Xiaowei Ren ,  Wayne R. Burger ,  Mark A. Bennett ,  Colin Kerr

发明人： Jeffrey K. Jones ,  Margaret A. Szymanowski ,  Michele L. Miera ,  Xiaowei Ren ,  Wayne R. Burger ,  Mark A. Bennett ,  Colin Kerr

IPC分类号： H01L21/768 ,  H01L23/488

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L29/0649 ,  H01L2224/05076 ,  H01L2224/05558 ,  H01L2224/05576 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).

摘要翻译： 具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少 作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。 由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有电绝缘的包含物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。 对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。 夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

公开(公告)号：US09225300B2

公开(公告)日：2015-12-29

申请号：US14265849

申请日：2014-04-30

申请人： Jeffrey K. Jones ,  Robert A. Pryor ,  Joseph G. Schultz

发明人： Jeffrey K. Jones ,  Robert A. Pryor ,  Joseph G. Schultz

IPC分类号： H03F1/56 ,  H03F3/19 ,  H03F3/21 ,  H03F3/191

CPC分类号： H03F1/56 ,  H03F3/19 ,  H03F3/191 ,  H03F3/193 ,  H03F3/21 ,  H03F3/211 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/451

摘要： A multiple-path, configurable, radio-frequency (RF) circuit is provided, including: a first amplifier path amplify a first RF signal to generate a first amplified signal; a second amplifier path configured to amplify a second RF signal to generate a second amplified signal; a corrective input matching circuit, configured to change first input-impedance-matching properties of the first amplifier path, and to change second input-impedance-matching properties of the second amplifier path; a first isolation element configured to selectively ground an input node of the second amplifier path; a second isolation element configured to selectively ground an output node of the second amplifier path; and a third isolation element connected between the first and second amplifier paths, configured to selectively isolate the corrective input matching circuit from first and second input nodes of the first and second amplifier paths, respectively, or connect the corrective input matching circuit to the first and second input nodes.

摘要翻译： 提供多路径，可配置的射频（RF）电路，包括：第一放大器路径放大第一RF信号以产生第一放大信号; 第二放大器路径，被配置为放大第二RF信号以产生第二放大信号; 校正输入匹配电路，被配置为改变第一放大器路径的第一输入阻抗匹配特性，并改变第二放大器路径的第二输入阻抗匹配特性; 第一隔离元件，被配置为选择性地接地第二放大器路径的输入节点; 第二隔离元件，被配置为选择性地接地所述第二放大器路径的输出节点; 以及连接在第一和第二放大器路径之间的第三隔离元件，被配置为分别将校正输入匹配电路与第一和第二放大器路径的第一和第二输入节点分离，或将校正输入匹配电路连接到第一和第二放大器路径 第二输入节点。

公开(公告)号：US20150262961A1

公开(公告)日：2015-09-17

申请号：US14204340

申请日：2014-03-11

申请人： Jeffrey K. Jones ,  Basim H. Noori ,  Mohd Salimin Sahludin ,  Fernando A. Santos

发明人： Jeffrey K. Jones ,  Basim H. Noori ,  Mohd Salimin Sahludin ,  Fernando A. Santos

IPC分类号： H01L23/00 ,  H01L29/861 ,  H01L23/64 ,  H01L27/07 ,  H01L21/822 ,  H01L49/02 ,  H01L27/06

CPC分类号： H01L24/48 ,  H01L21/822 ,  H01L22/14 ,  H01L23/642 ,  H01L23/647 ,  H01L24/43 ,  H01L24/45 ,  H01L27/0676 ,  H01L27/0794 ,  H01L28/20 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/13028 ,  H01L2224/1613 ,  H01L2224/438 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4801 ,  H01L2224/48011 ,  H01L2224/4813 ,  H01L2224/4847 ,  H01L2224/85399 ,  H01L2224/85423 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/20658 ,  H01L2924/30107 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756

摘要： A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.

摘要翻译： 半导体器件包括衬底，由衬底支撑并且通过间隙彼此间隔开的第一和第二接合焊盘结构，以及跨越间隙延伸并结合到第一和第二接合焊盘结构的引线接合脚跨接件。

公开(公告)号：US5018360A

公开(公告)日：1991-05-28

申请号：US538226

申请日：1990-06-14

申请人： Jeffrey K. Jones

发明人： Jeffrey K. Jones

IPC分类号： B44C5/00 ,  F25C1/12

CPC分类号： B44C5/00 ,  F25C1/12

摘要： Method and apparatus for creating and maintaining frosted sculptures are described. In a preferred embodiment, the apparatus includes an armature, or a length of conduit freely formed into a desirable shape, having circulated therethrough, by reverse-sublimation means operatively coupled therewith, a freezing agent. The reverse-sublimation means preferably includes pump means, condensation means and metering means, and is capable of removing the sensible heat and the latent heat of fusion from water vapor surrounding the armature, thereby to promote growth, on the exposed surface of the armature, of a thick layer of rough-textured frost.

摘要翻译： 描述了用于创建和维护磨砂雕塑的方法和装置。 在优选实施例中，该装置包括通过与其可操作地耦合的反向升华装置，自由形成为期望形状的衔铁或一定长度的导管，其通过其循环通过冷冻剂。 逆升华装置优选地包括泵装置，冷凝装置和计量装置，并且能够从电枢周围的水蒸气中除去显热和熔融潜热，从而促进在电枢的暴露表面上的生长， 一层粗糙的纹理霜冻。

公开(公告)号：US09438184B2

公开(公告)日：2016-09-06

申请号：US14317572

申请日：2014-06-27

申请人： Jeffrey K. Jones ,  Basim H. Noori ,  Michael E. Watts

发明人： Jeffrey K. Jones ,  Basim H. Noori ,  Michael E. Watts

IPC分类号： H01L21/8242 ,  H01L29/86 ,  H01L29/06 ,  H03F3/21 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H03F1/56 ,  H01L23/047 ,  H03F3/195 ,  H03F3/193

CPC分类号： H03F3/21 ,  H01G4/385 ,  H01G4/40 ,  H01L23/047 ,  H01L23/481 ,  H01L23/488 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/19104 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： An embodiment of an integrated passive device (IPD) assembly includes a first capacitor formed over a semiconductor substrate, where the first capacitor includes a first capacitor electrode, a second capacitor electrode, and dielectric material that electrically insulates the first capacitor electrode from the second capacitor electrode. The IPD assembly also includes a first contact pad exposed at a top surface of the IPD assembly and electrically coupled to the second capacitor electrode, and a second contact pad exposed at the top surface of the IPD. A second capacitor is coupled to the top surface of the IPD, and includes a first terminal electrically coupled to the first contact pad, and a second terminal electrically coupled to the second contact pad. The IPD assembly may be included in a packaged RF device, forming portions of an output impedance matching circuit and an envelope frequency termination circuit.

摘要翻译： 集成无源器件（IPD）组件的实施例包括形成在半导体衬底上的第一电容器，其中第一电容器包括第一电容器电极，第二电容器电极和将第一电容器电极与第二电容器电绝缘的电介质材料 电极。 IPD组件还包括暴露在IPD组件的顶表面处并电耦合到第二电容器电极的第一接触焊盘和暴露在IPD的顶表面处的第二接触焊盘。 第二电容器耦合到IPD的顶表面，并且包括电耦合到第一接触焊盘的第一端子和电耦合到第二接触焊盘的第二端子。 IPD组件可以包括在封装的RF器件中，形成输出阻抗匹配电路的一部分和封装频率终止电路。