公开(公告)号：US09117515B2

公开(公告)日：2015-08-25

申请号：US13352946

申请日：2012-01-18

Applicant: Feng-Ming Lee ,  Yu-Yu Lin

Inventor： Feng-Ming Lee ,  Yu-Yu Lin

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C8/10

CPC classification number: G11C13/0011 ,  G11C8/10 ,  G11C2213/54 ,  G11C2213/71 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.

Abstract translation: 可编程金属化器件包括第一电极和第二电极，以及在第一和第二电极之间串联的第一电介质层，第二电介质层和离子供给层。 在操作中，在第一电介质层中形成或破坏导电桥以表示数据值。 在读取期间，施加足以在第二电介质层中形成瞬态电桥的读取偏压，并且如果桥存在于第一介电层中，则形成通过电池的导电路径。 如果在读取期间桥不在第一电介质层中，则不形成导电路径。 在去除读取的偏置电压时，形成在第二介电层中的任何导电桥被破坏，而相应的其它第一介电层（如果有的话）中的导电桥保留。

公开(公告)号：US20130182487A1

公开(公告)日：2013-07-18

申请号：US13352946

申请日：2012-01-18

Applicant: FENG-MING LEE ,  Yu-Yu Lin

Inventor： FENG-MING LEE ,  Yu-Yu Lin

IPC: G11C11/00 ,  H01L21/822 ,  H01L27/08

CPC classification number: G11C13/0011 ,  G11C8/10 ,  G11C2213/54 ,  G11C2213/71 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.

Abstract translation: 可编程金属化器件包括第一电极和第二电极，以及在第一和第二电极之间串联的第一电介质层，第二电介质层和离子供给层。 在操作中，在第一电介质层中形成或破坏导电桥以表示数据值。 在读取期间，施加足以在第二电介质层中形成瞬态电桥的读取偏压，并且如果桥存在于第一介电层中，则形成通过电池的导电路径。 如果在读取期间桥不在第一电介质层中，则不形成导电路径。 在去除读取的偏置电压时，形成在第二介电层中的任何导电桥被破坏，而相应的其它第一介电层（如果有的话）中的导电桥保留。

公开(公告)号：US09437266B2

公开(公告)日：2016-09-06

申请号：US13675923

申请日：2012-11-13

Applicant: Feng-Ming Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

Inventor： Feng-Ming Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: H01L45/00 ,  G11C11/00 ,  H01L27/24

CPC classification number: G11C11/00 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract translation: 可编程金属化器件包括在第一和第二电极之间串联的第一电极和第二电极以及电介质层，导电离子阻挡层和离子供给层。 在操作中，在电介质层中形成或破坏导电桥，以使用具有相同极性的偏置电压来表示数据值，从而能够使用二极管接入装置。 为了形成导电桥，施加足够高的偏压，使得离子将导电离子阻挡层穿透到电介质层中，然后形成细丝或桥。 为了破坏导电桥，施加相同极性的偏压，导致电流流过结构，同时离子流被导电离子阻挡层阻挡。 作为焦耳加热的结果，介电层中的任何桥分解。

公开(公告)号：US08134139B2

公开(公告)日：2012-03-13

申请号：US12692861

申请日：2010-01-25

Applicant: Yu-Yu Lin ,  Feng-Ming Lee ,  Yi-Chou Chen

Inventor： Yu-Yu Lin ,  Feng-Ming Lee ,  Yi-Chou Chen

IPC: H01L29/18 ,  H01L21/06 ,  H01L45/00

CPC classification number: H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145

Abstract: A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Abstract translation: 可编程金属化器件，包括第一电极; 存储层，其电耦合到所述第一电极并适于通过其导电桥的电解形成和破坏; 离子供给层，其含有能够扩散到所述存储层中的第一金属元素的离子源; 在离子供给层和存储层之间的导电离子缓冲层，并且允许所述离子的扩散; 以及电耦合到所述离子供应层的第二电极。 电路耦合到器件以向第一和第二电极施加偏置电压，以引起包括存储器层中的第一金属元件的导电桥的产生和破坏。 离子缓冲层可以通过降低第一金属元素被吸收到离子供给层中的可能性来改善导电桥的保留。

公开(公告)号：US20120146218A1

公开(公告)日：2012-06-14

申请号：US12929549

申请日：2011-02-01

Applicant: Longqiang Zu ,  Yu-Yu Lin

Inventor： Longqiang Zu ,  Yu-Yu Lin

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L23/16 ,  H01L23/041 ,  H01L23/3128 ,  H01L23/66 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device with a cavity structure comprises: a carrier substrate; a first die having an active surface and the pads thereon; a back surface of the first die is disposed on the carrier substrate; a second die having a top surface and a back surface and a cavity structure therein; the top surface of a second die is flipped to dispose on the first die, and the cavity structure is an inverse U-type to dispose between the active surface of the first die and the top surface of the second die; the wires is electrically connected the pads with the first connecting points; a package body encapsulated the first die, the second die, the wires, and the portion of the top surface of the carrier substrate; and the connecting components is disposed on the back surface of the carrier substrate and is electrically connected the second connecting points.

公开(公告)号：US20120032328A1

公开(公告)日：2012-02-09

申请号：US12923462

申请日：2010-09-23

Applicant: Yu-Yu Lin ,  Chung-Kai Wang ,  Li-Hua Lin

Inventor： Yu-Yu Lin ,  Chung-Kai Wang ,  Li-Hua Lin

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/13 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15151 ,  H01L2924/3641 ,  H01L2924/00

Abstract: A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carrier substrate and is formed passed through the carrier substrate; providing a chip having an active surface and a back surface, a plurality of pads is disposed on the periphery of the active surface and a plurality of connecting elements is disposed thereon; the active surface of chip is flipped and bonded on the circuit arrangement on the top surface of the carrier substrate, and the plurality of connecting elements is not covering the through hole; filling the underfilling material to encapsulate between the plurality of connecting elements and the top surface of the carrier substrate and to fill with the through hole; and performing a suction process to remove the air within the underfilling material between the plurality of connecting elements on the chip and the top surface of the carrier substrate, such that the underfilling material can completely encapsulate between the plurality of connecting elements on the chip and the top surface of the carrier surface.

Abstract translation: 提供一种封装半导体器件的方法，其包括：提供具有顶表面和背表面的载体衬底，在载体衬底的顶表面上设置电路装置，并且在载体衬底的中心附近设置通孔 并形成通过载体基板; 提供具有活性表面和背面的芯片，多个焊盘设置在有源表面的周边上，并且多个连接元件设置在其上; 芯片的有源表面被翻转并接合在载体基板的顶表面上的电路装置上，并且多个连接元件不覆盖通孔; 填充底填充材料以封装在多个连接元件和载体基板的顶表面之间并填充通孔; 并且进行抽吸处理以去除芯片上的多个连接元件和载体基板的顶表面之间的底部填充材料内的空气，使得底部填充材料可以完全封装在芯片上的多个连接元件和 载体表面的顶表面。

公开(公告)号：US20100327725A1

公开(公告)日：2010-12-30

申请号：US12492379

申请日：2009-06-26

Applicant: Yen-Yu Huang ,  Yu-Yu Lin ,  Yu-Chun Lin ,  Huai-Jen Lu ,  Wan-Chih Lin

Inventor： Yen-Yu Huang ,  Yu-Yu Lin ,  Yu-Chun Lin ,  Huai-Jen Lu ,  Wan-Chih Lin

IPC: H01J61/52

CPC classification number: F21V29/767 ,  F21K9/232 ,  F21V7/0025 ,  F21Y2107/30 ,  F21Y2115/10

Abstract: A light-emitting diode (LED) lamp and a polygonal heat-dissipation structure thereof are provided. The LED lamp includes a polygonal heat-dissipation unit and a lighting module. The polygonal heat-dissipation unit has a polygonal hollow column and fins. The fins and the lighting module are thermally disposed on an inner surface and an outer surface of the polygonal hollow column, respectively. Thus, heat generated by the lighting module is dissipated by the fins rapidly. As the fins are thermally disposed on the inner surface of the polygon hollow column instead of being exposed, the volume of the LED lamp can be minimized, and the look of the LED lamp also can be prettified.

Abstract translation: 提供了一种发光二极管（LED）灯及其多边形散热结构。 LED灯包括多边形散热单元和照明模块。 多边形散热单元具有多边形空心柱和翅片。 翅片和照明模块分别热分布在多边形中空柱的内表面和外表面上。 因此，照明模块产生的热量被散热片快速消散。 由于翅片被热设置在多边形中空柱的内表面上而不是暴露，所以可以使LED灯的体积最小化，并且LED灯的外观也可以被优化。

公开(公告)号：US09449909B2

公开(公告)日：2016-09-20

申请号：US13620225

申请日：2012-09-14

Applicant: Chin-Sung Lin ,  Li-Hua Lin ,  Yu-Yu Lin

Inventor： Chin-Sung Lin ,  Li-Hua Lin ,  Yu-Yu Lin

IPC: H05K3/34 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K3/3436 ,  Y10T156/1089 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.

Abstract translation: 根据实施例，一种方法包括在其上提供具有导电材料的基板，从导电材料形成接地平面，第一迹线轨道和第一垂直迹线，以及在接地平面上形成绝缘体材料，第一 轨迹轨迹和第一条垂直轨迹。 接地平面位于第一轨迹和衬底的区域之间，在该区域上将是模具。 第一轨迹沿接地平面的第一外边缘延伸，并且第一垂直迹线耦合到第一迹线轨道并且从第一轨迹线垂直延伸。

公开(公告)号：US09053949B2

公开(公告)日：2015-06-09

申请号：US13548311

申请日：2012-07-13

Applicant: Yu-Yu Lin

Inventor： Yu-Yu Lin

IPC: H01L23/10 ,  H01L25/065 ,  H01L23/367 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L25/0655 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2225/1005 ,  H01L2924/014

Abstract: The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die.

Abstract translation: 本发明提供一种半导体器件及其相关方法，其包括衬底，第一裸片，围绕第一裸片的多个子封装系统和散热器。 第一模具和子包装系统安装在基板的相同表面上，其中第一模具和表面上的每个子封装系统的突出部分重叠，并且具有不重叠的部分。 每个子封装系统包括通过倒装芯片安装在插入器上的插入器和多个第二裸片。 散热器包括突出部分和散热板; 散热板覆盖第一模具和子封装体系，突起部分设置在散热板和第一模具之间。

公开(公告)号：US20140036570A1

公开(公告)日：2014-02-06

申请号：US13567750

申请日：2012-08-06

Applicant: Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

Inventor： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: G11C7/00 ,  G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/77

Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Abstract translation: 提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。 存储器件的操作方法包括以下步骤。 使存储器件处于置位状态。 用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。 读取设置状态的存储器件。 一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。 将恢复的偏置电压施加到存储器件。 在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。