公开(公告)号：US08642384B2

公开(公告)日：2014-02-04

申请号：US13417034

申请日：2012-03-09

申请人： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

发明人： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

摘要翻译： 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US20130234318A1

公开(公告)日：2013-09-12

申请号：US13417034

申请日：2012-03-09

申请人： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

发明人： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

摘要翻译： 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US10096540B2

公开(公告)日：2018-10-09

申请号：US13107075

申请日：2011-05-13

申请人： KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang ,  JaeHyun Lee

发明人： KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang ,  JaeHyun Lee

IPC分类号： H01L23/498 ,  H01L21/50 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

摘要： A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

公开(公告)号：US20130069221A1

公开(公告)日：2013-03-21

申请号：US13234366

申请日：2011-09-16

申请人： JaeHyun Lee ,  KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang

发明人： JaeHyun Lee ,  KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05186 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0665

摘要： A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate.

摘要翻译： 半导体器件具有安装到衬底的半导体管芯。 在半导体管芯上形成多个导电柱。 多个导电突起形成在导电柱上。 凸起形成在导电突起和导电柱上。 或者，导电突起形成在衬底上。 导电层形成在衬底上。 半导体管芯通过在小于导电柱和导电突起的熔点的温度下回流焊接而安装到衬底上，以将凸点冶金和电连接到导电层，同时保持半导体管芯和半导体管芯之间的固定偏移 基质。 半导体管芯和衬底之间的固定偏移由导电柱的高度和导电突起的高度决定。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US20120286418A1

公开(公告)日：2012-11-15

申请号：US13107075

申请日：2011-05-13

申请人： KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang ,  JaeHyun Lee

发明人： KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang ,  JaeHyun Lee

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03013 ,  H01L2224/0332 ,  H01L2224/0343 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/2929 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

摘要翻译： 半导体器件具有形成在半导体管芯的有效表面上的绝缘层的半导体管芯。 导电层形成在与主动表面电连接的第一绝缘层上。 多个导电柱形成在导电层上。 在与导电层和导电柱电隔离的第一绝缘层上形成多个虚拟柱。 将半导体管芯安装到基板上。 虚拟柱的高度大于导电柱的高度，以保持半导体管芯和衬底之间的间隔距离。 虚拟柱可以形成在衬底上。 虚拟柱设置在半导体管芯的角部和半导体管芯的中心区域。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US09230933B2

公开(公告)日：2016-01-05

申请号：US13234366

申请日：2011-09-16

申请人： JaeHyun Lee ,  KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang

发明人： JaeHyun Lee ,  KyungHoon Lee ,  SeongWon Park ,  KiYoun Jang

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05186 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0665

摘要： A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate.

摘要翻译： 半导体器件具有安装到衬底的半导体管芯。 在半导体管芯上形成多个导电柱。 多个导电突起形成在导电柱上。 凸起形成在导电突起和导电柱上。 或者，导电突起形成在衬底上。 导电层形成在衬底上。 半导体管芯通过在小于导电柱和导电突起的熔点的温度下回流焊接而安装到衬底上，以将凸点冶金和电连接到导电层，同时保持半导体管芯和半导体管芯之间的固定偏移 基质。 半导体管芯和衬底之间的固定偏移由导电柱的高度和导电突起的高度决定。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US20130105967A1

公开(公告)日：2013-05-02

申请号：US13287006

申请日：2011-11-01

申请人： JaeHyun Lee ,  KiYoun Jang

发明人： JaeHyun Lee ,  KiYoun Jang

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49894 ,  H01L21/4846 ,  H01L21/563 ,  H01L24/27 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/00

摘要： A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate. A first portion of the patterning layer is removed to form an opening to expose the substrate and conductive layer. A second portion of the patterning layer is removed to form a sloped surface in the patterning layer extending from a surface of the patterning layer down to the substrate. The sloped surface in the patterning layer can be linear, concave, or convex. The die is mounted to the substrate with the composite bump structures electrically connected to the conductive layer. An underfill material is deposited over the surface of the patterning layer. The sloped surface in the patterning layer aids with the flow of underfill material to cover an area between the die and substrate.

摘要翻译： 半导体器件具有在半导体管芯的表面上的复合凸块结构的半导体管芯。 在衬底上形成导电层。 在衬底上形成图形层。 去除图形层的第一部分以形成开口以暴露衬底和导电层。 图案化层的第二部分被去除以在图案形成层中形成从图案形成层的表面向下延伸到衬底的倾斜表面。 图案化层中的倾斜表面可以是线性的，凹的或凸的。 模具安装到基板上，复合凸块结构电连接到导电层。 在图案化层的表面上沉积底部填充材料。 图案化层中的倾斜表面有助于底部填充材料的流动以覆盖管芯和基底之间的区域。

公开(公告)号：US09054100B2

公开(公告)日：2015-06-09

申请号：US13287006

申请日：2011-11-01

申请人： JaeHyun Lee ,  KiYoun Jang

发明人： JaeHyun Lee ,  KiYoun Jang

IPC分类号： H01L21/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49894 ,  H01L21/4846 ,  H01L21/563 ,  H01L24/27 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/00

摘要： A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate. A first portion of the patterning layer is removed to form an opening to expose the substrate and conductive layer. A second portion of the patterning layer is removed to form a sloped surface in the patterning layer extending from a surface of the patterning layer down to the substrate. The sloped surface in the patterning layer can be linear, concave, or convex. The die is mounted to the substrate with the composite bump structures electrically connected to the conductive layer. An underfill material is deposited over the surface of the patterning layer. The sloped surface in the patterning layer aids with the flow of underfill material to cover an area between the die and substrate.

摘要翻译： 半导体器件具有在半导体管芯的表面上的复合凸块结构的半导体管芯。 在衬底上形成导电层。 在衬底上形成图形层。 去除图形层的第一部分以形成开口以暴露衬底和导电层。 图案化层的第二部分被去除以在图案形成层中形成从图案形成层的表面向下延伸到衬底的倾斜表面。 图案化层中的倾斜表面可以是线形，凹形或凸形。 模具安装到基板上，复合凸块结构电连接到导电层。 在图案化层的表面上沉积底部填充材料。 图案化层中的倾斜表面有助于底部填充材料的流动以覆盖管芯和基底之间的区域。

公开(公告)号：US09202715B2

公开(公告)日：2015-12-01

申请号：US13298267

申请日：2011-11-16

申请人： YoungChul Kim ,  KyungHoon Lee ,  Seong Won Park ,  Ki Youn Jang ,  JaeHyun Lee ,  DeokKyung Yang ,  In Sang Yoon ,  SungEun Park

发明人： YoungChul Kim ,  KyungHoon Lee ,  Seong Won Park ,  Ki Youn Jang ,  JaeHyun Lee ,  DeokKyung Yang ,  In Sang Yoon ,  SungEun Park

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 将连接柱附接到所述基板，所述连接柱具有柱顶和柱侧; 在基板上安装集成电路管芯，集成电路管芯具有顶部管芯表面; 以及在所述基板，所述连接柱和所述集成电路管芯上形成封装体。

公开(公告)号：US20120119360A1

公开(公告)日：2012-05-17

申请号：US13298267

申请日：2011-11-16

申请人： YoungChul Kim ,  KyungHoon Lee ,  Seong Won Park ,  Ki Youn Jang ,  JaeHyun Lee ,  DeokKyung Yang ,  In Sang Yoon ,  SungEun Park

发明人： YoungChul Kim ,  KyungHoon Lee ,  Seong Won Park ,  Ki Youn Jang ,  JaeHyun Lee ,  DeokKyung Yang ,  In Sang Yoon ,  SungEun Park

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 将连接柱附接到所述基板，所述连接柱具有柱顶和柱侧; 在基板上安装集成电路管芯，集成电路管芯具有顶部管芯表面; 以及在所述基板，所述连接柱和所述集成电路管芯上形成封装体。