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公开(公告)号：US20100105174A1
公开(公告)日：2010-04-29
申请号：US12652311
申请日：2010-01-05
申请人： Kuniharu Muto , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
发明人： Kuniharu Muto , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
IPC分类号： H01L21/60
CPC分类号： H01L23/49582 , H01L23/49503 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/544 , H01L24/05 , H01L24/29 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/77 , H01L24/78 , H01L24/83 , H01L24/84 , H01L24/85 , H01L29/0615 , H01L29/41766 , H01L29/456 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05624 , H01L2224/0603 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/37124 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/4912 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/78 , H01L2224/83801 , H01L2224/8385 , H01L2224/84205 , H01L2224/85205 , H01L2224/85207 , H01L2224/85214 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/83205 , H01L2924/206
摘要： To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
摘要翻译： 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。
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公开(公告)号：US20080265386A1
公开(公告)日：2008-10-30
申请号：US12057328
申请日：2008-03-27
申请人： Kuniharu MUTO , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
发明人： Kuniharu MUTO , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
IPC分类号： H01L23/495
CPC分类号： H01L23/49582 , H01L23/49503 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/544 , H01L24/05 , H01L24/29 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/77 , H01L24/78 , H01L24/83 , H01L24/84 , H01L24/85 , H01L29/0615 , H01L29/41766 , H01L29/456 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05624 , H01L2224/0603 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/37124 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/4912 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/78 , H01L2224/83801 , H01L2224/8385 , H01L2224/84205 , H01L2224/85205 , H01L2224/85214 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/83205
摘要： To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
摘要翻译： 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。
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公开(公告)号：US20120034742A1
公开(公告)日：2012-02-09
申请号：US13276995
申请日：2011-10-19
申请人： Kuniharu Muto , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
发明人： Kuniharu Muto , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
IPC分类号： H01L21/50
CPC分类号： H01L23/49582 , H01L23/49503 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/544 , H01L24/05 , H01L24/29 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/77 , H01L24/78 , H01L24/83 , H01L24/84 , H01L24/85 , H01L29/0615 , H01L29/41766 , H01L29/456 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05624 , H01L2224/0603 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/37124 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/4912 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/78 , H01L2224/83801 , H01L2224/8385 , H01L2224/84205 , H01L2224/85205 , H01L2224/85207 , H01L2224/85214 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/83205 , H01L2924/206
摘要： To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
摘要翻译： 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。
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公开(公告)号：US07667307B2
公开(公告)日：2010-02-23
申请号：US12057328
申请日：2008-03-27
申请人： Kuniharu Muto , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
发明人： Kuniharu Muto , Toshiyuki Hata , Hiroshi Sato , Hiroi Oka , Osamu Ikeda
IPC分类号： H01L23/495
CPC分类号： H01L23/49582 , H01L23/49503 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/544 , H01L24/05 , H01L24/29 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/77 , H01L24/78 , H01L24/83 , H01L24/84 , H01L24/85 , H01L29/0615 , H01L29/41766 , H01L29/456 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05624 , H01L2224/0603 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/37124 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/4912 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/78 , H01L2224/83801 , H01L2224/8385 , H01L2224/84205 , H01L2224/85205 , H01L2224/85214 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/83205
摘要： To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
摘要翻译： 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。
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公开(公告)号：US07220617B2
公开(公告)日：2007-05-22
申请号：US11349219
申请日：2006-02-08
申请人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
发明人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
CPC分类号： H01L23/24 , H01L21/52 , H01L23/488 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L2224/05155 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/16 , H01L2224/16245 , H01L2224/32245 , H01L2224/40225 , H01L2224/73153 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.
摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅极电极和源极电极与金属板端子接合。 此外，半导体芯片被树脂密封体密封，金属板端子的安装表面露出。 金属板端子和金属盖的第三部分的安装表面与安装板上的电极接合。
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公开(公告)号：US20060175700A1
公开(公告)日：2006-08-10
申请号：US11349219
申请日：2006-02-08
申请人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
发明人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
IPC分类号： H01L23/34
CPC分类号： H01L23/24 , H01L21/52 , H01L23/488 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L2224/05155 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/16 , H01L2224/16245 , H01L2224/32245 , H01L2224/40225 , H01L2224/73153 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.
摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅极电极和源极电极，并且栅极电极和源极电极与金属板端子接合。此外，半导体芯片由树脂密封体 金属板端子的安装表面露出。 金属板端子和金属盖的第三部分的安装表面与安装板上的电极接合。
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公开(公告)号：US20080268577A1
公开(公告)日：2008-10-30
申请号：US12164625
申请日：2008-06-30
申请人： Hidemasa KAGII , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
发明人： Hidemasa KAGII , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
IPC分类号： H01L21/00
CPC分类号： H01L23/24 , H01L21/52 , H01L23/488 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L2224/05155 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/16 , H01L2224/16245 , H01L2224/32245 , H01L2224/40225 , H01L2224/73153 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.
摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。
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公开(公告)号：US20070210430A1
公开(公告)日：2007-09-13
申请号：US11783919
申请日：2007-04-13
申请人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
发明人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
IPC分类号： H01L23/02
CPC分类号： H01L23/24 , H01L21/52 , H01L23/488 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L2224/05155 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/16 , H01L2224/16245 , H01L2224/32245 , H01L2224/40225 , H01L2224/73153 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.
摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。
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公开(公告)号：US07405469B2
公开(公告)日：2008-07-29
申请号：US11783919
申请日：2007-04-13
申请人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
发明人： Hidemasa Kagii , Akira Muto , Ichio Shimizu , Katsuo Arai , Hiroshi Sato , Hiroyuki Nakamura , Masahiko Osaka , Takuya Nakajo , Keiichi Okawa , Hiroi Oka
IPC分类号： H01L23/495
CPC分类号： H01L23/24 , H01L21/52 , H01L23/488 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L2224/05155 , H01L2224/05166 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/16 , H01L2224/16245 , H01L2224/32245 , H01L2224/40225 , H01L2224/73153 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.
摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。
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公开(公告)号：US08183607B2
公开(公告)日：2012-05-22
申请号：US13189883
申请日：2011-07-25
申请人： Ryoichi Kajiwara , Masahiro Koizumi , Toshiaki Morita , Kazuya Takahashi , Munehisa Kishimoto , Shigeru Ishii , Toshinori Hirashima , Yasushi Takahashi , Toshiyuki Hata , Hiroshi Sato , Keiichi Ookawa
发明人： Ryoichi Kajiwara , Masahiro Koizumi , Toshiaki Morita , Kazuya Takahashi , Munehisa Kishimoto , Shigeru Ishii , Toshinori Hirashima , Yasushi Takahashi , Toshiyuki Hata , Hiroshi Sato , Keiichi Ookawa
CPC分类号： H01L23/49555 , H01L21/4814 , H01L21/56 , H01L21/561 , H01L21/565 , H01L23/28 , H01L23/3107 , H01L23/495 , H01L23/4952 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L23/49582 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/83 , H01L24/84 , H01L24/97 , H01L29/7833 , H01L2224/0401 , H01L2224/04026 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/16245 , H01L2224/29011 , H01L2224/29015 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40225 , H01L2224/45124 , H01L2224/45139 , H01L2224/73253 , H01L2224/75251 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2224/83101 , H01L2224/83138 , H01L2224/83191 , H01L2224/83825 , H01L2224/8385 , H01L2224/83851 , H01L2224/84801 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/18301 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H05K3/3426 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/01049 , H01L2924/01083 , H01L2224/29139 , H01L2924/3512 , H01L2224/48 , H01L2924/00012
摘要： A semiconductor device features a semiconductor chip including a MOSFET, a first electrode of the MOSFET disposed on an obverse surface of the chip, a second, control electrode of the MOSFET disposed on the obverse surface, a third electrode of the MOSFET disposed on a second, opposing surface of the chip, first, second, and third conductive members, each having top surface and opposing bottom surface, the first, second, and third conductive members connecting with the first, second, and third electrodes electrically, respectively, a sealing body having top and bottom surfaces and sealing parts of the first, second, and third conductive members, the first conductive member having first, second, and third contiguous portions, the first portion is positioned over the first electrode, the second is positioned between the first and second portions and the third portion is positioned under the obverse surface of the chip.
摘要翻译： 半导体器件具有包括MOSFET的半导体芯片，设置在芯片的正面上的MOSFET的第一电极，设置在正面的MOSFET的第二控制电极，设置在第二个MOSFET上的MOSFET的第三电极 分别具有顶表面和相对的底表面的芯片，第一，第二和第三导电构件的相对表面，第一，第二和第三导电构件分别与第一，第二和第三电极电连接，密封 本体具有第一，第二和第三导电构件的顶表面和底表面和密封部分，第一导电构件具有第一，第二和第三邻接部分，第一部分位于第一电极上方，第二部分位于第 第一和第二部分，并且第三部分位于芯片的正面下方。
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