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1.发明授权Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form 有权半导体器件和将半导体管芯以复原晶片形式接合到衬底的方法公开(公告)号：US09287204B2
公开(公告)日：2016-03-15
申请号：US14039092
申请日：2013-09-27
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , KooHong Lee , JaeHak Yee , YoungChul Kim , Lan Hoang , Pandi C. Marimuthu , Steve Anderson , HunTeak Lee , HeeJo Chi
CPC classification number: H01L24/97 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/78 , H01L23/3128 , H01L23/3142 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11002 , H01L2224/1134 , H01L2224/13023 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/73204 , H01L2224/7598 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/83102 , H01L2224/83192 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00 , H01L2224/11 , H01L2924/00014 , H01L2924/0665 , H01L2924/00012
Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.
Abstract translation: 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。
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公开(公告)号：US09245772B2
公开(公告)日：2016-01-26
申请号：US14328348
申请日：2014-07-10
Applicant: STATS ChipPAC, Ltd.
Inventor： JoungIn Yang , ChoongBin Yim , KeonTeak Kang , YoungChul Kim
CPC classification number: H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/02 , H01L24/28 , H01L24/29 , H01L24/45 , H01L24/48 , H01L25/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/16 , H01L2224/16235 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2224/48611 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48711 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/83192 , H01L2224/83805 , H01L2224/85205 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2924/00011 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19107 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2224/13111 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/83205
Abstract: A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.
Abstract translation: 半导体封装包括衬底，安装到衬底的第一半导体管芯和通过第一粘合剂直接结合到第一半导体管芯的第一双面模具（DSM）内部可堆叠模块（ISM）。 第一DSM ISM包括第一模塑料和设置在第一模塑料中的第二半导体模。 半导体封装还包括耦合在第一半导体管芯和衬底之间的第一电连接以及耦合在第一DSM ISM和衬底之间的第二电连接。
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3.发明授权Semiconductor device and method of simultaneous molding and thermalcompression bonding 有权同时成型和热压缩粘合的半导体器件和方法公开(公告)号：US09245770B2
公开(公告)日：2016-01-26
申请号：US14038339
申请日：2013-09-26
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , KooHong Lee , JaeHak Yee , YoungChul Kim , Lan Hoang , Pandi C. Marimuthu , Steve Anderson , HeeJo Chi
CPC classification number: H01L21/56 , H01L21/565 , H01L23/3128 , H01L23/3192 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/94 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16057 , H01L2224/16058 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81484 , H01L2224/81907 , H01L2224/8191 , H01L2224/83192 , H01L2224/92 , H01L2224/9211 , H01L2224/94 , H01L2924/00011 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/11 , H01L2924/00015 , H01L2924/00014 , H01L2924/01082 , H01L2924/0105 , H01L2924/01047 , H01L2924/01083 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2224/81805
Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.
Abstract translation: 半导体器件具有设置在衬底上的半导体管芯。 将半导体管芯和衬底放置在追逐模具中。 在半导体管芯和衬底之上和之间沉积密封剂，同时将半导体管芯与追逐模具中的衬底结合。 通过施加力和升高的温度，使用热压将半导体管芯结合到衬底上。 在半导体管芯上方形成电连接结构，例如凸块，柱凸块或凸块。 焊剂材料沉积在互连结构上。 在基板的导电层上沉积焊膏或SOP。 焊剂材料和SOP在半导体管芯和衬底之间提供临时粘结。 互连结构与SOP结合。 或者，互连结构可以直接结合到衬底的导电层，具有或不具有焊剂材料。
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公开(公告)号：US20140319702A1
公开(公告)日：2014-10-30
申请号：US14328348
申请日：2014-07-10
Applicant: STATS ChipPAC, Ltd.
Inventor： JoungIn Yang , ChoongBin Yim , KeonTeak Kang , YoungChul Kim
CPC classification number: H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/02 , H01L24/28 , H01L24/29 , H01L24/45 , H01L24/48 , H01L25/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/16 , H01L2224/16235 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2224/48611 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48711 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/83192 , H01L2224/83805 , H01L2224/85205 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2924/00011 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19107 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2224/13111 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/83205
Abstract: A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.
Abstract translation: 半导体封装包括衬底，安装到衬底的第一半导体管芯和通过第一粘合剂直接结合到第一半导体管芯的第一双面模具（DSM）内部可堆叠模块（ISM）。 第一DSM ISM包括第一模塑料和设置在第一模塑料中的第二半导体模。 半导体封装还包括耦合在第一半导体管芯和衬底之间的第一电连接以及耦合在第一DSM ISM和衬底之间的第二电连接。
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5.发明申请Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form 有权半导体器件和将半导体晶片结合到重构晶片形式的衬底的方法公开(公告)号：US20140175640A1
公开(公告)日：2014-06-26
申请号：US14039092
申请日：2013-09-27
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , KooHong Lee , JaeHak Yee , YoungChul Kim , Lan Hoang , Pandi C. Marimuthu , Steve Anderson , HunTeak Lee , HeeJo Chi
IPC: H01L23/498 , H01L21/56
CPC classification number: H01L24/97 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/78 , H01L23/3128 , H01L23/3142 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11002 , H01L2224/1134 , H01L2224/13023 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/73204 , H01L2224/7598 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/83102 , H01L2224/83192 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00 , H01L2224/11 , H01L2924/00014 , H01L2924/0665 , H01L2924/00012
Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.
Abstract translation: 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。
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Patent Agency Ranking
6.发明授权公开(公告)号：US09252130B2
公开(公告)日：2016-02-02
申请号：US13853810
申请日：2013-03-29
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , YoungChul Kim , HunTeak Lee , KeonTaek Kang , HeeJo Chi
IPC: H01L25/065 , H01L23/31 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1134 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/2919 , H01L2224/32225 , H01L2224/48145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73207 , H01L2224/75251 , H01L2224/75252 , H01L2224/75704 , H01L2224/75705 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83192 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/12043 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2224/83 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.
Abstract translation: 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。
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7.发明授权Semiconductor device and method of making bumpless flipchip interconnect structures 有权半导体器件和制造无凸块的倒装芯片互连结构的方法公开(公告)号：US09240331B2
公开(公告)日：2016-01-19
申请号：US14039418
申请日：2013-09-27
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , KooHong Lee , JaeHak Yee , YoungChul Kim , Lan Hoang , Pandi C. Marimuthu , Steve Anderson , See Chian Lim , HeeJo Chi
IPC: H01L23/52 , H01L29/40 , H01L21/48 , H01L23/00 , H01L23/498
CPC classification number: H01L21/4867 , H01L23/49811 , H01L23/49816 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0381 , H01L2224/0401 , H01L2224/05567 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05684 , H01L2224/10165 , H01L2224/13076 , H01L2224/131 , H01L2224/13294 , H01L2224/13311 , H01L2224/13313 , H01L2224/13316 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13794 , H01L2224/138 , H01L2224/16112 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/1701 , H01L2224/17517 , H01L2224/48091 , H01L2224/73265 , H01L2224/81007 , H01L2224/81011 , H01L2224/81022 , H01L2224/81024 , H01L2224/8114 , H01L2224/81192 , H01L2224/81201 , H01L2224/81203 , H01L2224/81424 , H01L2224/81815 , H01L2224/81986 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/81805
Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.
Abstract translation: 半导体器件包括具有接触焊盘的衬底。 掩模设置在基板上。 铝可润湿的导电浆料印刷在基材的接触垫上。 将半导体管芯设置在铝可润湿的导电膏上。 铝可湿性导电膏被回流以在衬底的接触焊盘上形成互连结构。 接触垫包括铝。 半导体管芯的接触焊盘设置在铝可润湿的导电膏上。 铝可润湿的导电膏被回流以在半导体管芯的接触焊盘和衬底的接触焊盘之间形成互连结构。 互连结构直接形成在基板和半导体管芯的接触焊盘上。 在回流铝可湿性导电膏之前，蚀刻半导体管芯的接触焊盘。 环氧预处理点，以保持半导体管芯和衬底之间的间隔。
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8.发明申请Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding 有权使用双面热压缩接合制造倒装芯片半导体封装的方法公开(公告)号：US20140295618A1
公开(公告)日：2014-10-02
申请号：US13853810
申请日：2013-03-29
Applicant: STATS CHIPPAC, LTD.
Inventor： KyungMoon Kim , YoungChul Kim , HunTeak Lee , KeonTaek Kang , HeeJo Chi
IPC: H01L23/00
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1134 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/2919 , H01L2224/32225 , H01L2224/48145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73207 , H01L2224/75251 , H01L2224/75252 , H01L2224/75704 , H01L2224/75705 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83192 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/12043 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2224/83 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.
Abstract translation: 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。
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9.发明申请Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures 有权半导体器件及制作无铅片式互连结构的方法公开(公告)号：US20140175661A1
公开(公告)日：2014-06-26
申请号：US14039418
申请日：2013-09-27
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , KooHong Lee , JaeHak Yee , YoungChul Kim , Lan Hoang , Pandi C. Marimuthu , Steve Anderson , See Chian Lim , HeeJo Chi
CPC classification number: H01L21/4867 , H01L23/49811 , H01L23/49816 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0381 , H01L2224/0401 , H01L2224/05567 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05684 , H01L2224/10165 , H01L2224/13076 , H01L2224/131 , H01L2224/13294 , H01L2224/13311 , H01L2224/13313 , H01L2224/13316 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13794 , H01L2224/138 , H01L2224/16112 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/1701 , H01L2224/17517 , H01L2224/48091 , H01L2224/73265 , H01L2224/81007 , H01L2224/81011 , H01L2224/81022 , H01L2224/81024 , H01L2224/8114 , H01L2224/81192 , H01L2224/81201 , H01L2224/81203 , H01L2224/81424 , H01L2224/81815 , H01L2224/81986 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/81805
Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.
Abstract translation: 半导体器件包括具有接触焊盘的衬底。 掩模设置在基板上。 铝可润湿的导电膏被印刷在基底的接触垫上。 将半导体管芯设置在铝可润湿的导电膏上。 铝可湿性导电膏被回流以在衬底的接触焊盘上形成互连结构。 接触垫包括铝。 半导体管芯的接触焊盘设置在铝可润湿的导电膏上。 铝可润湿的导电膏被回流以在半导体管芯的接触焊盘和衬底的接触焊盘之间形成互连结构。 互连结构直接形成在基板和半导体管芯的接触焊盘上。 在回流铝可湿性导电膏之前，蚀刻半导体管芯的接触焊盘。 环氧预处理点，以保持半导体管芯和衬底之间的间隔。
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10.发明申请Semiconductor Device and Method of Simultaneous Molding and Thermalcompression Bonding 有权同时成型和热压缩接合的半导体器件和方法公开(公告)号：US20140175639A1
公开(公告)日：2014-06-26
申请号：US14038339
申请日：2013-09-26
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , KooHong Lee , JaeHak Yee , YoungChul Kim , Lan Hoang , Pandi C. Marimuthu , Steve Anderson , HeeJo Chi
IPC: H01L23/498 , H01L21/56
CPC classification number: H01L21/56 , H01L21/565 , H01L23/3128 , H01L23/3192 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/94 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16057 , H01L2224/16058 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81484 , H01L2224/81907 , H01L2224/8191 , H01L2224/83192 , H01L2224/92 , H01L2224/9211 , H01L2224/94 , H01L2924/00011 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/11 , H01L2924/00015 , H01L2924/00014 , H01L2924/01082 , H01L2924/0105 , H01L2924/01047 , H01L2924/01083 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2224/81805
Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.
Abstract translation: 半导体器件具有设置在衬底上的半导体管芯。 将半导体管芯和衬底放置在追逐模具中。 在半导体管芯和衬底之上和之间沉积密封剂，同时将半导体管芯与追逐模具中的衬底结合。 通过施加力和升高的温度，使用热压将半导体管芯结合到衬底上。 在半导体管芯上方形成电连接结构，例如凸块，柱凸块或凸块。 焊剂材料沉积在互连结构上。 在基板的导电层上沉积焊膏或SOP。 焊剂材料和SOP在半导体管芯和衬底之间提供临时粘结。 互连结构与SOP结合。 或者，互连结构可以直接结合到衬底的导电层，具有或不具有助焊剂材料。
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