公开(公告)号：US11342253B2

公开(公告)日：2022-05-24

申请号：US16684774

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10 ,  H01L23/00

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US10304700B2

公开(公告)日：2019-05-28

申请号：US15170487

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Shih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US09786617B2

公开(公告)日：2017-10-10

申请号：US14942267

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2224/83

Abstract: A chip package may include a die and a redistribution structure over the die. The redistribution structure may include a die, a redistribution structure over the die, and an under-bump metallurgy (UBM) structure over the redistribution structure. The UBM structure may include a central portion, a peripheral portion physically separated from and surrounding a perimeter of the central portion, and a bridging portion having a first end and a second end opposite the first end. The first end of the bridging portion may be coupled to the central portion of the UBM structure, while the second end of the bridging portion may be coupled to the peripheral portion of the UBM structure.

公开(公告)号：US09748188B2

公开(公告)日：2017-08-29

申请号：US14934634

申请日：2015-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Cheng Kuo ,  Chita Chuang ,  Chen-Shien Chen ,  Yao-Chun Chuang

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/49 ,  H01L29/00 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/488 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

公开(公告)号：US09196573B2

公开(公告)日：2015-11-24

申请号：US13733692

申请日：2013-01-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Chun Chuang ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/488 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L23/488 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Abstract translation: 上述实施例提供了封装和接合基板之间的结合结构的扩大的重叠表面积。 通过在封装和/或接合衬底上使用细长的结合结构并且通过使这种结合结构定向，结合结构被设计成承受由热循环引起的结合应力以减少冷接头。

公开(公告)号：US08829673B2

公开(公告)日：2014-09-09

申请号：US13667306

申请日：2012-11-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Hong Cha ,  Chita Chuang ,  Yao-Chun Chuang ,  Hao-Juin Liu ,  Tsung-Hsien Chiang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76897 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract translation: 所描述的实施例提供了在基本上面向封装结构的中心的铜柱的侧面上没有焊料润湿的封装结构的边缘附近的细长结合结构。 焊接润湿发生在这些结合结构的铜柱的另一侧。 细长结合结构被布置成不同的布置并且减小相邻结合结构之间短路的机会。 另外，细长的结合结构提高了可靠性。

公开(公告)号：US20140231994A1

公开(公告)日：2014-08-21

申请号：US14266231

申请日：2014-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Chun Chuang ,  Ching-Wen Hsiao ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01083 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00

Abstract: An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper.

Abstract translation: 一种装置包括具有形成在其上的铜的至少一个输入/输出端子的集成电路。 金属盖层覆盖在至少一个输入/输出端子的上表面上。 衬底包括形成在第一表面上的至少一个导电迹线，并且金属光洁度层覆盖至少一个导电迹线的一部分。 在金属盖层和金属表面层之间设置无铅焊料连接，第一金属间化合物设置在金属盖层和无铅焊料连接之间的界面处。 无铅焊料的铜含量小于0.5wt。 ％，第一金属间化合物基本上不含铜。

公开(公告)号：US08772950B2

公开(公告)日：2014-07-08

申请号：US13671284

申请日：2012-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chita Chuang ,  Yao-Chun Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L29/74 ,  H01L31/111

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/585 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed.

Abstract translation: 具有保护环的倒装芯片基板的方法和装置。 实施例包括具有用于附接集成电路管芯的管芯附着区域的衬底芯; 覆盖所述基板芯的裸片侧表面的至少一个介电层; 以及至少一个保护环，其形成在所述衬底芯的角部附近，所述至少一个保护环包括：覆盖所述电介质层的第一迹线，所述第一迹线具有从所述衬底芯的角部沿两个方向延伸并且平行于所述边缘的矩形部分 的衬底芯; 位于介电层下面的第二个迹线; 以及至少一个通孔延伸穿过介电层并耦合第一和第二迹线; 其中所述第一迹线，所述至少一个通孔和所述第二迹线形成垂直通孔叠层。 公开了用保护环形成倒装芯片基板的方法。

公开(公告)号：US20130288473A1

公开(公告)日：2013-10-31

申请号：US13925924

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Chun Chuang ,  Chang-Chia Huang ,  Tsung-Shu Lin ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05086 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.

公开(公告)号：US20130249091A1

公开(公告)日：2013-09-26

申请号：US13899216

申请日：2013-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

IPC: H01L23/498

CPC classification number: H01L24/11 ,  H01L23/485 ,  H01L23/498 ,  H01L23/49811 ,  H01L24/27 ,  H01L2224/05552 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction.

Abstract translation: 集成电路结构包括具有第一区域和第二区域的半导体芯片; 形成在半导体芯片的第一区域和第二区域上的电介质层; 形成在所述电介质层中且在所述半导体芯片的所述第一区域上并且具有沿第一方向延伸的第一长轴的第一细长凹凸金属化（UBM）连接器; 以及第二细长UBM连接器，其形成在所述半导体芯片的所述第二区域上的所述电介质层中，并且具有沿第二方向延伸的第二长轴。 第一个方向与第二个方向不同。