公开(公告)号：US5508232A

公开(公告)日：1996-04-16

申请号：US386808

申请日：1995-02-06

申请人： Tetsuya Ueda ,  Kazunari Michii ,  Yutaka Koyama ,  Naoto Ueda

发明人： Tetsuya Ueda ,  Kazunari Michii ,  Yutaka Koyama ,  Naoto Ueda

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L21/565 ,  H01L23/49537 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49121

摘要： In a method of manufacturing a semiconductor device, overlaid on a first lead frame including a die pad supported by a plurality of die pad suspending leads is a second lead frame having connecting leads wherein the first and second lead frames are disposed on a first molding die such that the die pad and inner lead portions of the inner leads of the second lead frame are accommodated within a first cavity of the first molding die while offset portions of the die pad suspending leads are disposed outside of the first cavity. A second molding die is clamped onto the first molding die to define a resin molding chamber which is then filled with a molten resin to form a package. After removing the package from the first and second molding dies, the offset portions are cut away from the package while cutting the connecting leads to a predetermined length. A semiconductor chip as large as permissible can be embedded within a semiconductor device of a standard size while ensuring high quality and improved reliability of the semiconductor device.

摘要翻译： 在制造半导体器件的方法中，覆盖在包括由多个管芯焊盘悬挂引线支撑的管芯焊盘的第一引线框架上的是具有连接引线的第二引线框架，其中第一引线框架和第二引线框架设置在第一成型模具 使得第二引线框架的内引线的管芯焊盘和内引线部分容纳在第一成型模具的第一腔内，同时将芯片垫悬挂引线的偏移部分设置在第一腔体的外部。 将第二成型模具夹在第一模具上以限定树脂模制室，然后用熔融树脂填充以形成包装。 在从第一和第二模具中取出包装之后，将连接引线切割成​​预定长度，将偏移部分从包装中切出。 可以将尺寸大的半导体芯片嵌入到标准尺寸的半导体器件中，同时确保半导体器件的高品质和可靠性。

公开(公告)号：USRE35496E

公开(公告)日：1997-04-29

申请号：US525174

申请日：1995-09-08

申请人： Ken Yamamura ,  Naoto Ueda ,  Kazunari Michii ,  Hitoshi Fujimoto ,  Kiyoaki Tsumura ,  Hitoshi Sasaki ,  Takashi Miyamoto

发明人： Ken Yamamura ,  Naoto Ueda ,  Kazunari Michii ,  Hitoshi Fujimoto ,  Kiyoaki Tsumura ,  Hitoshi Sasaki ,  Takashi Miyamoto

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/495 ,  H01L23/02 ,  H01L23/08 ,  H01L43/00

CPC分类号： H01L24/85 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/78 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30105 ,  Y10T29/49146 ,  Y10T29/49158 ,  Y10T29/49169 ,  Y10T29/49171

摘要： A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms pan of a resin package.

摘要翻译： 本发明的半导体器件在小尺寸封装中容纳大型半导体芯片，而不损害其可靠性。 半导体芯片被接合在相对较小的管芯焊盘上。 通常的内部引线和多个内部引线与半导体芯片相对设置并间隔0.1mm至0.4mm的间隙，并且半导体芯片与公共内部引线之间的间隙以及多个内部引线填充有 形成树脂包装盘的树脂。

公开(公告)号：US5334803A

公开(公告)日：1994-08-02

申请号：US968055

申请日：1992-10-28

申请人： Ken Yamamura ,  Naoto Ueda ,  Kazunari Michii ,  Hitoshi Fujimoto ,  Kiyoaki Tsumura ,  Hitoshi Sasaki ,  Takashi Miyamoto

发明人： Ken Yamamura ,  Naoto Ueda ,  Kazunari Michii ,  Hitoshi Fujimoto ,  Kiyoaki Tsumura ,  Hitoshi Sasaki ,  Takashi Miyamoto

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/495 ,  H01L23/02 ,  H01L23/28 ,  H01R43/00

CPC分类号： H01L24/85 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/78 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30105 ,  Y10T29/49146 ,  Y10T29/49158 ,  Y10T29/49169 ,  Y10T29/49171

摘要： A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms part of a resin package.

摘要翻译： 本发明的半导体器件在小尺寸封装中容纳大型半导体芯片，而不损害其可靠性。 半导体芯片被接合在相对较小的管芯焊盘上。 通常的内引线和多个内引线与半导体芯片相对设置并间隔0.1mm至0.4mm的间隙，并且半导体芯片与公共内引线之间的间隙和多个内引线填充有 形成树脂封装的一部分的树脂。

公开(公告)号：US5196917A

公开(公告)日：1993-03-23

申请号：US444973

申请日：1989-12-04

申请人： Tetsuya Ueda ,  Kou Shimomura ,  Osamu Nakagawa ,  Seiji Takemura ,  Kazunari Michii

发明人： Tetsuya Ueda ,  Kou Shimomura ,  Osamu Nakagawa ,  Seiji Takemura ,  Kazunari Michii

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/48

CPC分类号： H01L23/48 ,  H01L2224/16

摘要： A carrier tape includes an insulating film supporting a plurality of leads. The film has a center device hole for receiving a semiconductor chip therein, a plurality of outer lead holes formed at the periphery of the center device hole, a lead supporting portion positioned between the center device hole and the outer lead holes, and a link portion positioned between a pair of adjacent outer lead holes and connected to the lead supporting portion for directing the flow of molten resin during encapsulation of the semiconductor chip. The link portion includes an opening or recess. The plurality of leads of the carrier tape are supported on the lead supporting of the film, with one end portion of each lead projecting into the center device hole of the film. During manufacture, a semiconductor chip having a plurality of electrodes is positioned within the center device hole, and the leads are electrically connected to respective electrodes of the semiconductor chip. The resultant chip is placed within a cavity of a mold, and a molten resin is injected into the cavity through the opening or recess passage formed in the link portion of the film.

摘要翻译： 载带包括支撑多根引线的绝缘膜。 薄膜具有用于容纳半导体芯片的中心装置孔，形成在中心装置孔周边的多个外部引线孔，位于中心装置孔和外部引线孔之间的引线支承部分，以及连接部分 定位在一对相邻的外引线孔之间并连接到引线支撑部分，用于在半导体芯片封装期间引导熔融树脂的流动。 连杆部分包括开口或凹槽。 载带的多个引线被支撑在膜的引线支撑上，每个引线的一个端部突出到膜的中心装置孔中。 在制造过程中，具有多个电极的半导体芯片位于中心器件孔内，引线与半导体芯片的各个电极电连接。 将所得的芯片放置在模具的空腔内，并且通过形成在薄膜的连接部分中的开口或凹槽通道将熔融树脂注入空腔中。

公开(公告)号：US20060240596A1

公开(公告)日：2006-10-26

申请号：US11473081

申请日：2006-06-23

申请人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

发明人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

摘要翻译： 多个半导体芯片安装在用于制造半导体器件的基板的表面上。 半导体芯片被树脂共同密封，从而形成树脂密封部。 在基板的背面形成有多个焊球，使得相邻的半导体芯片的相应的焊锡球之间的间隔A成为“n”倍（“n”为大于1的整数）焊料间的间隔B 半导体芯片上的球。 在半导体芯片进行电气测试之后，将树脂密封部分和基板切片，从而将半导体芯片分解成块。

公开(公告)号：US06670701B2

公开(公告)日：2003-12-30

申请号：US10000031

申请日：2001-12-04

申请人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii ,  Hajime Maeda

发明人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii ,  Hajime Maeda

IPC分类号： H01L2302

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/15311 ,  H05K1/144 ,  H05K1/145 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/1572

摘要： A semiconductor module achieving higher density of the semiconductor module itself as well as of being disposed in an area-efficient manner relative to another electronic component, such as a mother board and the like. The semiconductor module includes a mounting substrate having, on an underside, a solder ball for connecting to an interconnection of a mother board and semiconductor packages mounted in multiple layers on the top side of the mounting substrate and connected to electrodes on the mounting substrate.

摘要翻译： 实现半导体模块本身的更高密度以及相对于诸如母板等的其他电子部件以区域有效的方式设置的半导体模块。 该半导体模块包括安装基板，其在下侧具有用于连接到母板和安装在安装基板的顶侧上的多层的半导体封装的互连的焊球，并连接到安装基板上的电极。

公开(公告)号：US06518652B2

公开(公告)日：2003-02-11

申请号：US09808151

申请日：2001-03-15

申请人： Yasuki Takata ,  Hiroshi Horibe ,  Kazunari Michii

发明人： Yasuki Takata ,  Hiroshi Horibe ,  Kazunari Michii

IPC分类号： H01L23495

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85447 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor chip, a die pad, an adhesive, metal wires, LOC inner leads, and standard inner leads sealed within a sealing resin. The LOC inner leads and the standard inner leads are arranged in the same plane and both are arranged along one side of the semiconductor chip. Clearance between the inner leads and the die pad larger than the total thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed can be employed and the section modulus of the semiconductor package can be increased.

摘要翻译： 半导体封装包括半导体芯片，芯片焊盘，粘合剂，金属线，LOC内引线和密封在密封树脂内的标准内引线。 LOC内引线和标准内引线布置在同一平面中，并且都沿着半导体芯片的一侧布置。 内引线和芯片焊盘之间的间隙大于半导体芯片和接合材料的总厚度。 因此，可以采用具有广泛分布的电极焊盘的半导体芯片，并且可以增加半导体封装的截面模数。

公开(公告)号：US5373188A

公开(公告)日：1994-12-13

申请号：US3422

申请日：1993-01-12

申请人： Kazunari Michii ,  Koichi Nakagawa

发明人： Kazunari Michii ,  Koichi Nakagawa

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/32 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/82181 ,  H01L2224/85181 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107

摘要： A resin-molded multi-chip package semiconductor device includes a lead frame having a plurality of leads including crossing leads that extend over an obverse or a reverse side of one semiconductor element separated from electrical contact with the element by an interposed insulating material. The electrodes of one element and of another element are electrically connected in common to the crossing lead by bonding wires. The device may comprise a TAB tape having leads on an insulating tape, electrically connecting the electrodes of the neighboring elements together. The TAB tape may include crossing leads that cross another TAB lead.

摘要翻译： 树脂模制的多芯片封装半导体器件包括引线框架，该引线框架具有多个引线，引线包括跨越一个半导体元件的正面或反面的交叉引线，该半导体元件通过插入的绝缘材料与元件电接触而分离。 一个元件的电极和另一个元件的电极通过接合线电连接到交叉引线。 该装置可以包括在绝缘带上具有引线的TAB带，将相邻元件的电极电连接在一起。 TAB带可以包括穿过另一TAB引线的交叉引线。

公开(公告)号：US06798056B2

公开(公告)日：2004-09-28

申请号：US10231148

申请日：2002-08-30

申请人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii

发明人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii

IPC分类号： H01L2302

CPC分类号： H05K1/181 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K7/026 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

摘要： A semiconductor module includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the former. The pad electrodes connected to the leads of these semiconductor packages are arranged alternately. The lead has a dambar residual portion. An inner surface of a lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of a lead downward portion of the lower layer semiconductor package.

摘要翻译： 半导体模块包括：表面上具有焊盘电极的基板，安装在基板上的下层半导体封装，以及安装在基板上的上层半导体封装，同时布置在基本上覆盖前者的位置。 连接到这些半导体封装的引线的焊盘电极交替布置。 铅带有残渣部分。 上层半导体封装的引线向下部分的内表面位于下层半导体封装的引线向下部分的外表面的外侧。

公开(公告)号：US06614101B2

公开(公告)日：2003-09-02

申请号：US09579268

申请日：2000-05-26

申请人： Kazuyuki Misumi ,  Kazunari Michii ,  Manabu Horita

发明人： Kazuyuki Misumi ,  Kazunari Michii ,  Manabu Horita

IPC分类号： H01L23495

CPC分类号： H01L24/06 ,  H01L23/49503 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A plastic packaged semiconductor device is constructed by sealing, with a sealing plastic, a semiconductor chip which has an electrode pad arranged in a central portion of an upper surface, a die pad to which the semiconductor chip is die-bonded, bonding wires which are connected to the electrode pad, and inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces which are positioned at a level equal to or higher than the upper surface of the semiconductor chip and to which the bonding wires are connected. Accordingly, the small thin plastic packaged semiconductor device in which the bonding wires do never come into contact with the edge of the semiconductor chip can be achieved.

摘要翻译： 塑料封装半导体器件通过密封塑料制成，半导体芯片具有布置在上表面的中心部分的电极焊盘，半导体芯片被芯片接合的芯片焊盘， 连接到电极焊盘和布置在芯片焊盘附近的内部引线，并且具有顶部部分，其顶部部分具有位于等于或高于半导体芯片的上表面的电平的上部平坦表面， 电线连接。 因此，可以实现其中接合线不会与半导体芯片的边缘接触的小型薄塑料封装半导体器件。