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    PRESSURE REGULATOR
    1.
    发明申请
    PRESSURE REGULATOR 审中-公开
    压力调节器

    公开(公告)号：US20110048553A1

    公开(公告)日：2011-03-03

    申请号：US11996955

    申请日：2006-07-25

    申请人： Yasuaki Nakamura ,  Hideto Usui ,  Satoshi Kamiyama ,  Mitsuo Hirotomi

    发明人： Yasuaki Nakamura ,  Hideto Usui ,  Satoshi Kamiyama ,  Mitsuo Hirotomi

    IPC分类号： F16K7/00

    CPC分类号： G05D16/0661 ,  Y10T137/7904

    摘要： A pressure regulator includes a housing having an inlet port through which pressurized fluid at a primary pressure is supplied, and a discharge port through which pressurized fluid at a secondary pressure lower than the primary pressure is discharged, and at the same time having a flow passage formed therein to extend from the inlet port to the discharge port, and a pressure control mechanism which is disposed on the flow passage to reduce the primary pressure to the secondary pressure. The pressure control mechanism includes a movable body including a diaphragm which is displaced in response to change in the pressure of the fluid and the movable body is provided with an abutment portion which is brought into abutment against a part of the housing to prevent the movable body from being excessively displaced when the primary pressure becomes excessively high.

    摘要翻译： 压力调节器包括壳体，该壳体具有供给初级压力的加压流体的入口端口以及排出低于初级压力的次级压力的加压流体的排出口，同时具有流路 形成在其中以从入口端口延伸到排放口;以及压力控制机构，其布置在流动通道上以将初级压力降低到次级压力。 压力控制机构包括：移动体，其包括响应于流体的压力变化而移位的隔膜，并且可移动体设置有邻接部分，抵靠部分抵靠壳体的一部分以防止移动体 当初级压力变得过高时，不会发生过度位移。

    Low barrier ohmic contact for semiconductor light emitting device
    5.
    发明授权
    Low barrier ohmic contact for semiconductor light emitting device 失效
    半导体发光器件的低阻挡欧姆接触

    公开(公告)号：US6087725A

    公开(公告)日：2000-07-11

    申请号：US161498

    申请日：1998-09-28

    申请人： Shigeo Yoshii ,  Yoichi Sasai ,  Satoshi Kamiyama ,  Tohru Saitoh ,  Takashi Nishikawa ,  Ryoko Miyanaga

    发明人： Shigeo Yoshii ,  Yoichi Sasai ,  Satoshi Kamiyama ,  Tohru Saitoh ,  Takashi Nishikawa ,  Ryoko Miyanaga

    IPC分类号： H01L33/28 ,  H01L33/40 ,  H01L33/00

    CPC分类号： H01L33/40 ,  H01L33/28

    摘要： On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.

    摘要翻译： 在n型GaAs的衬底上，n型Zn0.9Mg0.1S0.13Se0.87的n型覆层，n型ZnS0.06Se0.94的n型导光层，n型ZnS0.06Se0.94的有源层 ZnCdSe和p型ZnS0.06Se0.94的p型导光层依次形成。 在p型导光层上形成p型接触结构。 p型接触结构包括第一层p型ZnS0.31Se0.54Te0.15，第二层ZnS0.47Se0.28Te0.25，第三层p型ZnS0.65Te0.35，第四层 的p型ZnS0.5Te0.5和第五层p型ZnTe。

    Method of fabricating capacitor element in super-LSI
    8.
    发明授权
    Method of fabricating capacitor element in super-LSI 失效
    超LSI制造电容元件的方法

    公开(公告)号：US5438012A

    公开(公告)日：1995-08-01

    申请号：US102634

    申请日：1993-08-05

    申请人： Satoshi Kamiyama

    发明人： Satoshi Kamiyama

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L28/40

    摘要： A capacitor element of a semiconductor device used for a super-LSI is formed by the steps including (a) removing a natural oxide film on a surface of a lower electrode of polysilicon, (b) forming on the surface of the lower electrode an impurity-doped tantalum oxide film, and (c) forming an upper electrode with at least a bottom thereof constituted by titanium nitride. The steps may further include (d) nitriding the surface of the lower electrode after the removal of the natural oxide film, and (e) densifying the tantalum oxide film by way of a high temperature heat treatment after the formation of the tantalum oxide film. In this way, it is possible to reduce thickness of a capacitive insulating film and to form the capacitor element in which the leakage current characteristics are improved.

    摘要翻译： 用于超级LSI的半导体器件的电容器元件通过以下步骤形成，所述步骤包括：（a）在多晶硅的下电极的表面上去除自然氧化物膜，（b）在下电极的表面上形成杂质 掺杂的氧化钽膜，（c）至少形成由氮化钛构成的底部的上部电极。 这些步骤还可以包括（d）在去除天然氧化物膜之后氮化下电极的表面，和（e）在氧化钽膜形成之后通过高温热处理使氧化钽膜致密化。 以这种方式，可以减小电容绝缘膜的厚度并形成其中泄漏电流特性得到改善的电容器元件。

    Method for manufacturing a semiconductor device
    9.
    发明授权
    Method for manufacturing a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US5352623A

    公开(公告)日：1994-10-04

    申请号：US196486

    申请日：1994-02-15

    申请人： Satoshi Kamiyama

    发明人： Satoshi Kamiyama

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10852 ,  H01L28/40

    摘要： A method for manufacturing a semiconductor device, wherein a thin film of tantalum oxide is formed as a dielectric film in a capacitor element, increases capacitance per unit area and reduces a leakage current in the capacitor element of DRAM memory cells. The method includes steps of forming a polysilicon film constituting a lower electrode of the capacitor element, removing a natural oxide film from the surface of the polysilicon film, nitriding the surface of the polysilicon by rapid thermal nitriding (RTN) using lamp-annealing, forming a tantalum oxide film, densifying and nitriding consecutively the tantalum oxide film, and forming an upper capacitor electrode thereon. The capacitor element formed by the method has a large capacitance per unit area Cs=13.8 fF/.mu.m.sup.2.

    摘要翻译： 一种用于制造半导体器件的方法，其中在电容器元件中形成氧化钽薄膜作为电介质膜，增加了每单位面积的电容，并降低了DRAM存储单元的电容器元件中的漏电流。 该方法包括以下步骤：形成构成电容器元件的下电极的多晶硅膜，从多晶硅膜的表面去除自然氧化膜，通过使用灯退火的快速热氮化（RTN）对多晶硅的表面进行氮化，形成 氧化钽膜，连续致密化氮化钽膜，在其上形成上层电容电极。 由该方法形成的电容器元件具有单位面积Cs = 13.8fF / m 2的大电容。

    Anti-guided phase-locked array and manufacturing method therefor
    10.
    发明授权
    Anti-guided phase-locked array and manufacturing method therefor 失效
    反引导锁相阵列及其制造方法

    公开(公告)号：US5323405A

    公开(公告)日：1994-06-21

    申请号：US953359

    申请日：1992-09-30

    申请人： Satoshi Kamiyama ,  Kiyoshi Ohnaka

    发明人： Satoshi Kamiyama ,  Kiyoshi Ohnaka

    IPC分类号： H01L27/15 ,  H01S5/00 ,  H01S5/042 ,  H01S5/20 ,  H01S5/40 ,  H01S3/082 ,  H01S3/098 ,  H01S3/25

    CPC分类号： H01S5/4031 ,  H01S5/2059

    摘要： A phase-locked laser array comprising a plurality of element regions for passing electric current into an active layer; and inter-element regions formed between the element regions. Each of the inter-element regions is so formed as to have two regions, i.e. a non-diffusion region at the center thereof and a diffusion regions disposed on both sides thereof, thereby rendering the refractive index in the non-diffusion region higher than that in the diffusion regions. The method of manufacturing the phase-locked laser array which is characterized by including a step growing an optical waveguide layer of superlattice on a portion of a second clad layer while diffusing impurities doped in the second clad layer into said optical waveguide layer, thereby forming a diffusion regions on both sides of the inter-element region.

    摘要翻译： 一种锁相激光器阵列，包括用于将电流传递到有源层中的多个元件区域; 以及形成在元件区域之间的元件间区域。 每个元件间区域被形成为具有两个区域，即其中心处的非扩散区域和设置在其两侧的扩散区域，从而使非扩散区域中的折射率高于不扩散区域的折射率 在扩散区域。 制造锁相激光器阵列的方法，其特征在于包括在第二包覆层的一部分上生长超晶格的光波导层的步骤，同时将掺杂在第二包层中的杂质扩散到所述光波导层中，从而形成 扩散区域在元件间区域的两侧。