公开(公告)号：US20110084383A1

公开(公告)日：2011-04-14

申请号：US12903403

申请日：2010-10-13

Applicant: Daisuke MIZUTANI

Inventor： Daisuke MIZUTANI

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H05K1/147 ,  H01L21/76898 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/222 ,  H05K3/3436 ,  H05K3/363 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09063 ,  H05K2201/092 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.

Abstract translation: 半导体器件包括：第一电路基体部件，其包括形成有多个第一电极的表面;第二电路基体部件，设置在第一电路基体的上方，并具有分别形成在第一电极上方的第一通孔和第二通孔; 设置在第二电路基体上方的封装，以及设置在第一通孔内的多个第一凸起和第二通孔，以将第一电极连接到半导体封装。

公开(公告)号：US07851707B2

公开(公告)日：2010-12-14

申请号：US11591559

申请日：2006-11-02

Applicant: Daisuke Mizutani ,  Tatsuhiko Tajima

Inventor： Daisuke Mizutani ,  Tatsuhiko Tajima

IPC: H05K1/03

CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  Y10T29/49126

Abstract: A circuit board for reducing a transmission loss and a method for manufacturing the circuit board. In the circuit board including a ground layer and power layer facing each other, a wiring layer disposed between the ground layer and the power layer, and an insulating section formed between the ground layer and the power layer so as to sandwich the wiring layer therebetween, a low dielectric loss layer having a dielectric tangent lower than that of the insulating section is formed at least on an upper or lower surface of the wiring layer. According to such a circuit board, the low dielectric loss layer is formed on an interface between the insulating section and the wiring layer, and therefore, a transmission loss in a high frequency region is reduced.

Abstract translation: 一种用于降低传输损耗的电路板和一种用于制造电路板的方法。 在包括接地层和功率层相对的电路板中，布置在接地层和功率层之间的布线层以及形成在接地层和功率层之间以将布线层夹在其间的绝缘部分， 至少在布线层的上表面或下表面上形成具有低于绝缘部分的介电切线的低介电损耗层。 根据这种电路板，低介电损耗层形成在绝缘部分和布线层之间的界面上，因此降低了高频区域的传输损耗。

公开(公告)号：US6001488A

公开(公告)日：1999-12-14

申请号：US106179

申请日：1998-06-29

Applicant: Hideaki Kataoka ,  Eiko Yuda ,  Shigemitsu Kamiya ,  Masahide Yamamoto ,  Yoshikatsu Ishizuki ,  Yasuhiro Yoneda ,  Daisuke Mizutani ,  Kishio Yokouchi

Inventor： Hideaki Kataoka ,  Eiko Yuda ,  Shigemitsu Kamiya ,  Masahide Yamamoto ,  Yoshikatsu Ishizuki ,  Yasuhiro Yoneda ,  Daisuke Mizutani ,  Kishio Yokouchi

IPC: C08F283/14 ,  C08G59/32 ,  C08G59/34 ,  C08G61/08 ,  C08L51/08 ,  G03F7/004 ,  G03F7/012 ,  G03F7/038 ,  H01B3/40 ,  H01B3/44 ,  B32B27/04 ,  B32B27/28 ,  C08F255/08 ,  C08L51/06

CPC classification number: C08G59/027 ,  C08F283/14 ,  C08G59/3218 ,  C08G61/08 ,  C08L51/08 ,  G03F7/0045 ,  G03F7/0125 ,  G03F7/038 ,  H01B3/40 ,  H01B3/441 ,  Y10S428/901 ,  Y10T428/31663

Abstract: A resin composition comprising an epoxy group-containing cycloolefin resin and a crosslinking agent is provided. More specifically, a resin composition comprising an epoxy group-containing thermoplastic norbornene resin obtained by introducing epoxy groups into a thermoplastic norbornene resin, and as the crosslinking agent, a curing agent for epoxy resins or a photoreactive substance is provided. The resin composition is suitable for use as an insulating material.

Abstract translation: 提供了包含含环氧基的环烯烃树脂和交联剂的树脂组合物。 更具体地说，提供一种包含通过将环氧基引入到热塑性降冰片烯树脂中而获得的含环氧基的热塑性降冰片烯树脂和作为交联剂的环氧树脂或光反应性物质的固化剂的树脂组合物。 树脂组合物适合用作绝缘材料。

公开(公告)号：US20110089579A1

公开(公告)日：2011-04-21

申请号：US12902527

申请日：2010-10-12

Applicant: Masateru KOIDE ,  Daisuke MIZUTANI ,  Aiichiro INOUE ,  Hideo YAMASHITA ,  Iwao YAMAZAKI ,  Masayuki KATO ,  Seiji UENO ,  Kazuyuki IMAMURA

Inventor： Masateru KOIDE ,  Daisuke MIZUTANI ,  Aiichiro INOUE ,  Hideo YAMASHITA ,  Iwao YAMAZAKI ,  Masayuki KATO ,  Seiji UENO ,  Kazuyuki IMAMURA

IPC: H01L23/52

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/0001 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract translation: 多芯片模块包括：板; 布线板，其布置在所述板上并且包括布线图案; 以及配置在配线基板上的多个芯片。 多个芯片中的每一个与其他芯片中的至少一个连接，并且多个芯片和板通过布线板的布线图案之外的部分彼此电连接。

公开(公告)号：US20110080717A1

公开(公告)日：2011-04-07

申请号：US12887600

申请日：2010-09-22

Applicant: Masateru KOIDE ,  Daisuke Mizutani

Inventor： Masateru KOIDE ,  Daisuke Mizutani

IPC: H05K1/11 ,  H01L21/50

CPC classification number: H05K1/141 ,  H01L23/142 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/445 ,  H05K2201/10378 ,  H05K2201/10477 ,  H01L2224/0401

Abstract: An interconnect board for interconnecting and arranged between a first circuit board and a second circuit board, the interconnect board includes a conductive plate including a connection terminal to be electrically connected to a power supply terminal or a ground terminal of each of the first circuit board and the second circuit board, an insulating member wrapping the conductive plate except for the connection terminal, and a conductive member penetrating the insulating member to electrically connect a signal terminal of the first circuit board to a signal terminal of the second circuit board.

Abstract translation: 一种用于互连并布置在第一电路板和第二电路板之间的互连板，所述互连板包括导电板，所述导电板包括电连接到所述第一电路板的电源端子或接地端子的连接端子，以及 所述第二电路板，除了所述连接端子之外包覆所述导电板的绝缘构件以及穿过所述绝缘构件的导电构件将所述第一电路板的信号端子电连接到所述第二电路板的信号端子。

公开(公告)号：US20110042806A1

公开(公告)日：2011-02-24

申请号：US12857884

申请日：2010-08-17

Applicant: Masateru Koide ,  Daisuke Mizutani

Inventor： Masateru Koide ,  Daisuke Mizutani

IPC: H01L23/538 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method of manufacturing a multi-chip module includes: securing a plurality of chips on a surface of a flat-shaped member through a solder bump; connecting the plurality of chips with each other by a bonding wire, at surfaces, opposite to the flat-shaped member side, of the plurality of chips; and electrically connecting the plurality of chips with a board, at the surfaces, opposite to the flat-shaped member side, of the plurality of chips.

Abstract translation: 一种制造多芯片模块的方法包括：通过焊料凸块将多个芯片固定在平坦构件的表面上; 通过接合线在多个芯片的与平面形状构件侧相对的表面处将多个芯片彼此连接; 以及在所述多个芯片的与所述平坦构件侧相对的表面处，将所述多个芯片与板电连接。

公开(公告)号：US07791197B2

公开(公告)日：2010-09-07

申请号：US12068593

申请日：2008-02-08

Applicant: Daisuke Mizutani

Inventor： Daisuke Mizutani

IPC: H01L23/488

CPC classification number: H05K3/4007 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/10152 ,  H01L2224/13099 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H05K1/113 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49147 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element.

Abstract translation: 半导体器件具有具有多个连接端子的半导体元件，与半导体元件电连接的电路基板; 以及布置在所述半导体元件和所述电路基板之间的连接构件，所述连接构件具有多个具有柱状部分的导电突起，每个所述柱状部分与每个连接端子连接，所述柱状部分沿着平行于 半导体元件的表面小于半导体元件的每个连接端子的表面积。

公开(公告)号：US20080022518A1

公开(公告)日：2008-01-31

申请号：US11591559

申请日：2006-11-02

Applicant: Daisuke Mizutani ,  Tatsuhiko Tajima

Inventor： Daisuke Mizutani ,  Tatsuhiko Tajima

IPC: H05K3/36 ,  B05D1/02 ,  H05K1/00

CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  Y10T29/49126

Abstract: A circuit board for reducing a transmission loss and a method for manufacturing the circuit board. In the circuit board including a ground layer and power layer facing each other, a wiring layer disposed between the ground layer and the power layer, and an insulating section formed between the ground layer and the power layer so as to sandwich the wiring layer therebetween, a low dielectric loss layer having a dielectric tangent lower than that of the insulating section is formed at least on an upper or lower surface of the wiring layer. According to such a circuit board, the low dielectric loss layer is formed on an interface between the insulating section and the wiring layer, and therefore, a transmission loss in a high frequency region is reduced.

Abstract translation: 一种用于降低传输损耗的电路板和一种用于制造电路板的方法。 在包括接地层和功率层相对的电路板中，布置在接地层和功率层之间的布线层以及形成在接地层和功率层之间以将布线层夹在其间的绝缘部分， 至少在布线层的上表面或下表面上形成具有低于绝缘部分的介电切线的低介电损耗层。 根据这种电路板，低介电损耗层形成在绝缘部分和布线层之间的界面上，因此降低了高频区域的传输损耗。

公开(公告)号：US20070221400A1

公开(公告)日：2007-09-27

申请号：US11486061

申请日：2006-07-14

Applicant: Mamoru Kurashina ,  Daisuke Mizutani

Inventor： Mamoru Kurashina ,  Daisuke Mizutani

IPC: H05K1/03

CPC classification number: H05K3/281 ,  H01L21/563 ,  H01L23/145 ,  H01L23/4922 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K3/4644 ,  H05K2201/029 ,  H01L2924/00

Abstract: A multilayer interconnection substrate includes a resin laminated structure in which plural build-up layers are laminated, each of the plural build-up layers comprising an insulation layer and an interconnection pattern, and first and second solder resist layers provided on a top surface and a bottom surface of the resin laminated structure, wherein each of the first and second solder resist layers includes a glass cloth.

Abstract translation: 多层互连基板包括层叠有多个堆积层的树脂层叠结构，所述多个堆积层中的每一个包括绝缘层和互连图案，以及设置在顶表面上的第一和第二阻焊层， 所述树脂层压结构的底表面，其中所述第一和第二阻焊层中的每一个包括玻璃布。

公开(公告)号：US07253023B2

公开(公告)日：2007-08-07

申请号：US11017785

申请日：2004-12-22

Applicant: Toshihiro Kusagaya ,  Yasuhiro Yoneda ,  Daisuke Mizutani ,  Kazuhiko Iijima ,  Yuji Suwa

Inventor： Toshihiro Kusagaya ,  Yasuhiro Yoneda ,  Daisuke Mizutani ,  Kazuhiko Iijima ,  Yuji Suwa

IPC: H01L21/44

CPC classification number: H05K3/4641 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/01087 ,  H05K1/0216 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1394

Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.

Abstract translation: 能够通过降低所提供的电路的电感来抑制在产生高频噪声的同时对电路进行高频开关动作的便宜的多层布线电路板。 一种多层布线电路板，包括：被指定为第一层的最上层，其上安装有部件; 布置有接地层和电源层中的一个的第二层; 另一个排列在其上的第三层; 以及布置在接地层和电源层之间的绝缘层。 作为在电源层和接地层之间配置的绝缘层的材料，使用两面具有热塑性粘合性的树脂层。