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    ELECTROLESS METAL THROUGH SILICON VIA
    1.
    发明申请
    ELECTROLESS METAL THROUGH SILICON VIA 审中-公开

    公开(公告)号：WO2014051511A3

    公开(公告)日：2014-04-03

    申请号：PCT/SE2013/051124

    申请日：2013-09-27

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS, Thorbjörn ,  KNUTSSON, Henrik

    IPC: H01L21/768 ,  H01L23/48 ,  H01L23/52

    Abstract: The invention relates to methods of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface. It comprises providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited Cu on the Ni by a plating process. Line widths and spacings

    METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE
    2.
    发明申请
    METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE 审中-公开
    提供通孔和路由结构的方法

    公开(公告)号：WO2013147694A1

    公开(公告)日：2013-10-03

    申请号：PCT/SE2013/050353

    申请日：2013-03-28

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS, Thorbjörn ,  PERTTU, Daniel

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76831 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a method of providing a via hole and routing structure. A a substrate wafer having recesses and blind holes provided in the surface of the wafer is provided. An insulating layer is provided in the recesses and the holes, and the holes and recesses are metallized. The oxide layer in the bottom of the holes is removed to provide a contact between the back side and the front side of the wafer. The invention also provides a semiconductor device, comprising a substrate having at least one metallized via (V) extending through the substrate and at least one metallized recess forming a routing (RDL) together with the via (V). There is an oxide layer (ISO) on the front side field and on the back side field. The metal in the recess (RDL) and the via (V) is flush with the oxide (ISO) on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is

    Abstract translation: 本发明涉及一种提供通孔和布线结构的方法。 提供了具有设置在晶片表面上的凹陷和盲孔的衬底晶片。 在凹部和孔中设置有绝缘层，并且孔和凹槽被金属化。 去除孔的底部中的氧化物层，以提供晶片的背侧和前侧之间的接触。 本发明还提供了一种半导体器件，其包括具有延伸穿过衬底的至少一个金属化通孔（V）的衬底和与通孔（V）一起形成路由（RDL）的至少一个金属化凹槽。 前侧场和背面场都有氧化层（ISO）。 凹槽（RDL）和通孔（V）中的金属至少在前侧与场上的氧化物（ISO）齐平，由此提供平坦的前侧。 半导体器件的厚度<300μm。

    VIA STRUCTURE AND METHOD THEREOF
    3.
    发明申请
    VIA STRUCTURE AND METHOD THEREOF 审中-公开
    通过其结构和方法

    公开(公告)号：WO2010074649A1

    公开(公告)日：2010-07-01

    申请号：PCT/SE2009/051496

    申请日：2009-12-23

    Applicant: SILEX MICROSYSTEMS AB ,  EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  ÅGREN, Peter ,  SVEDIN, Niklas

    Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  ÅGREN, Peter ,  SVEDIN, Niklas

    IPC: H01L23/522 ,  B61B7/00 ,  B81C1/00 ,  H01L21/768 ,  G02B26/08

    CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

    Abstract translation: 本发明涉及分层的微电子和/或微机械结构，其包括在导电层之间具有绝缘层的至少三个交替的导电层。 还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供 通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。 它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。 该装置具有根据本发明的分层结构。 还提供了制造这种分层MEMS结构的方法。

    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    5.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 审中-公开
    CTE匹配插件及其制作方法

    公开(公告)号：WO2013154497A4

    公开(公告)日：2014-01-23

    申请号：PCT/SE2013050408

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  PERTTU DANIEL

    IPC: H01L23/32 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The inventive merit of the present interposer is that it is possible to taylor the coefficient of thermal expansion CTE of the interposer to match components to be attached thereto within very wide ranges. The invention relates to a emiconductor interposer, comprising a substrate (10) of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer- through via (18, 28, 27) comprising metal (27). At least one recess (20)is provided in the first side of the substrate (10) and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure (20). The exposed surfaces of the metal filled via and the metal filled recess (18, 27) are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via (18, 28, 27) comprises a narrow part (18) and a wider part (27), and there are provided contact elements on said routing structure (20) having an aspect ratio, height:diameter,

    Abstract translation: 本插值器的优点在于，可以在非常宽的范围内使插入件的热膨胀系数CTE与要附着的部件相匹配。 本发明涉及一种具有第一侧（FS）和相对的第二侧（BS）的半导体材料的衬底（10）的半导体插入器。 存在至少一个包含金属（27）的导电晶片通孔（18,28,27）。 至少一个凹部（20）设置在基板（10）的第一侧面中，并且在基板的半导体材料中，凹槽填充有金属并与晶圆通孔连接，从而提供布线结构（20）。 填充通孔的金属和金属填充的凹槽（18,27）的暴露的表面基本上与衬底的第一侧上的衬底表面齐平。 晶片通孔（18,28,27）包括窄部分（18）和较宽部分（27），并且在所述布线结构（20）上设置有具有纵横比，高度：直径， 1：1，优选1：1至2：1。

    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    6.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 审中-公开
    CTE匹配插件及其制作方法

    公开(公告)号：WO2013154497A3

    公开(公告)日：2013-12-05

    申请号：PCT/SE2013050408

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  PERTTU DANIEL

    IPC: H01L23/32 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The inventive merit of the present interposer is that it is possible to taylor the coefficient of thermal expansion CTE of the interposer to match components to be attached thereto within very wide ranges. The invention relates to a emiconductor interposer, comprising a substrate (10) of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer- through via (18, 28, 27) comprising metal (27). At least one recess (20)is provided in the first side of the substrate (10) and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure (20). The exposed surfaces of the metal filled via and the metal filled recess (18, 27) are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via (18, 28, 27) comprises a narrow part (18) and a wider part (27), and there are provided contact elements on said routing structure (20) having an aspect ratio, height:diameter,

    Abstract translation: 本插值器的优点在于，可以在非常宽的范围内使插入件的热膨胀系数CTE与要附着的部件匹配。 本发明涉及一种具有第一侧（FS）和相对的第二侧（BS）的半导体材料的衬底（10）的半导体插入器。 存在包含金属（27）的至少一个导电晶片通孔（18,28,27）。 在衬底（10）的第一侧中提供至少一个凹部（20），并且在衬底的半导体材料中，凹部填充有金属并与晶片通孔连接，从而提供路由结构（20）。 金属填充通孔和金属填充凹槽（18,27）的暴露表面基本上与衬底的第一侧上的衬底表面齐平。 晶片通孔（18,28,27）包括窄部分（18）和较宽部分（27），并且在所述布线结构（20）上设置有具有纵横比，高度：直径， 1：1，优选1：1至2：1。

    THIN FILM CAPPING
    7.
    发明申请
    THIN FILM CAPPING 审中-公开
    薄膜覆盖

    公开(公告)号：WO2013089635A1

    公开(公告)日：2013-06-20

    申请号：PCT/SE2012/051402

    申请日：2012-12-17

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS, Thorbjörn ,  SVEDIN, Niklas

    IPC: B81C1/00

    CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145

    Abstract: The present invention relates to methods for sealing cavities in micro- electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity. The method comprises providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of said cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through said hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.

    Abstract translation: 本发明涉及用于在微电子/机械系统（MEMS）装置中密封空腔的方法，以在密封空腔内提供受控的气氛。 该方法包括提供其上在基板的局部区域上提供模板的半导体衬底。 模板限定了所述腔体的内部形状。 孔被制成以便能够排出空腔以提供期望的气氛以通过所述孔进入空腔。 最后，在孔中设置密封材料以密封空腔。 密封可以通过密封材料的压缩和/或熔化来制造。

    FABRICATION OF INLET AND OUTLET CONNECTIONS FOR MICROFLUIDIC CHIPS
    10.
    发明申请
    FABRICATION OF INLET AND OUTLET CONNECTIONS FOR MICROFLUIDIC CHIPS 审中-公开
    微流控芯片的入口和出口连接的制造

    公开(公告)号：WO2007043963A1

    公开(公告)日：2007-04-19

    申请号：PCT/SE2006/050381

    申请日：2006-10-05

    Applicant: SILEX MICROSYSTEMS AB ,  KÄLVESTEN, Edvard

    Inventor： KÄLVESTEN, Edvard

    IPC: B81C1/00 ,  B81B1/00

    CPC classification number: B81B7/0061 ,  B81B2201/058

    Abstract: The invention relates to a method of making a fluid communication channel between a micro mechanical structure provided on a front side of a device and the back side of said device. It comprises making the required structural components by lithographic and etching processes on said front side. Holes are then drilled from the back side of said device in precise alignment with the structures on said front side, to provide inlets and/or outlets to and/or from said micromechanical structure.

    Abstract translation: 本发明涉及在设置在设备的前侧的微机械结构与所述设备的背面之间制造流体连通通道的方法。 它包括在所述前侧通过光刻和蚀刻工艺制造所需的结构部件。 然后从所述装置的背面钻出孔，以与所述前侧上的结构精确对准，以向所述微机械结构提供入口和/或出口。

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