公开(公告)号：WO2005038876A2

公开(公告)日：2005-04-28

申请号：PCT/US2004/034067

申请日：2004-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MOTSIFF, William, T. ,  MUZZY, Christopher, D.

Inventor： MOTSIFF, William, T. ,  MUZZY, Christopher, D.

IPC: H01L

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and associated method for protecting an electrical structure (25) during a fuse link deletion by focused radiation (52). The structure (1 ) comprises a fuse element (2), a protection plate (10), a first dielectric layer (14), and a second dielectric layer (4). The structure (1) is formed within a semiconductor device (5). The protection plate (10) is formed within the first dielectric layer (14) using a damascene process. The second dielectric layer (4) is formed over the protection plate (10) and the first dielectric layer (14). The fuse element (2) is formed over the second dielectric layer (4). The fuse element (2) is adapted to be cut with a laser beam (52). The dielectric constant of the second dielectric layer (4) is greater than the dielectric constant of the first dielectric layer (14). The protection plate (10) is adapted to shield the first dielectric layer (14) from energy from the laser beam (52).

Abstract translation: 用于在通过聚焦辐射（52）删除熔丝链路期间保护电气结构（25）的结构和相关方法。 结构（1）包括熔丝元件（2），保护板（10），第一介电层（14）和第二介电层（4）。 结构（1）形成在半导体器件（5）内。 使用镶嵌工艺在第一介电层（14）内形成保护板（10）。 第二介电层（4）形成在保护板（10）和第一介电层（14）之上。 熔丝元件（2）形成在第二介电层（4）之上。 熔丝元件（2）适于用激光束（52）切割。 第二介电层（4）的介电常数大于第一介电层（14）的介电常数。 保护板（10）适于屏蔽第一电介质层（14）免受来自激光束（52）的能量。

公开(公告)号：WO2008100923A2

公开(公告)日：2008-08-21

申请号：PCT/US2008/053703

申请日：2008-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  SAUTER, Wolfgang

Inventor： DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  SAUTER, Wolfgang

IPC: H01L21/44

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/0501 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack (20') is deposited above a metal pad layer (19'). A top layer (22') of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer (21 ') of the barrier metal stack (20') removed by etching. The diffusion barrier (40) and C4 solder bump (50) may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Abstract translation: 用于消除当形成用于BLM（球限制冶金）的C4焊料凸点并且改善C4间距时消除底切的系统和方法。 在该工艺中，在金属垫层（19'）上方沉积阻挡层金属堆叠（20'）。 通过蚀刻去除阻挡金属堆叠（20'）的底部导电层（21'），通过CMP图案化阻挡层金属（例如，Cu）的顶层（22'）。 在一个实施例中，使用无掩模技术或通过使用图案化掩模的电镀技术，可以通过无电镀形成扩散阻挡层（40）和C4焊料凸块（50）。 这样可以减少C4焊料凸点的间距。

公开(公告)号：WO2007127816A3

公开(公告)日：2007-11-08

申请号：PCT/US2007/067449

申请日：2007-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FAROOQ, Mukta, G. ,  DAUBENSPECK, Timothy, H. ,  SAUTER, Wolfgang ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  PETRARCA, Kevin, S.

Inventor： FAROOQ, Mukta, G. ,  DAUBENSPECK, Timothy, H. ,  SAUTER, Wolfgang ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  PETRARCA, Kevin, S.

IPC: H01L21/44

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads 37 with ball limiting metallization on an integrated circuit chip 30 by using a damascene process and preferably Cu metallization 32 in the chip 30 and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad 52 is formed in the top insulating layer 51 and it also serves as the final level of metallization in the chip.

公开(公告)号：WO2014042811A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/055032

申请日：2013-08-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

IPC: H01L21/44 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer (4); a controlled collapse chip connection (C4) bump (10) overlying the PSPI layer; and a solder (18) overlying the C4 bump and contacting a side (20) of the C4 bump. The method can further include recessing a portion of the PSPI layer (4) adjacent to the C4 bump (10) to form a PSPI pedestal (26) under the C4 bump (10). The method can additionally include forming an Underfill (32) abutting the PSPI pedestal (26) and the C4 bump (10), wherein the Underfill (32) and the solder (18) form an interface separated from the PSPI pedestal (26).

Abstract translation: 各种实施方案包括形成互连结构的方法以及通过这些方法形成的结构。 在一个实施方案中，一种方法可以包括：提供具有光敏聚酰亚胺（PSPI）层（4）的前体互连结构; 覆盖PSPI层的可控崩溃芯片连接（C4）突起（10）; 以及覆盖C4凸起并且接触C4凸块的一侧（20）的焊料（18）。 该方法还可以包括使与C4凸块（10）相邻的PSPI层（4）的一部分凹陷以在C4凸块（10）下形成PSPI基座（26）。 该方法还可以包括形成邻接PSPI基座（26）和C4凸块（10）的底部填充物（32），其中底部填充物（32）和焊料（18）形成与PSPI基座（26）分离的界面。

公开(公告)号：WO2013074178A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/052749

申请日：2012-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

Inventor： DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

IPC: H01L23/48

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/02235 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06131 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012

Abstract: A topographical feature (305) is formed proximate to a conductive bond pad (235) that is used to couple a solder bump (160) to a semiconductor die (140). The topographical feature (305) is separated from the conductive bond pad (235) by a gap (310). In one embodiment, the topographical feature (305) is formed at a location that is slightly beyond the perimeter of the solder bump (160), wherein an edge of the bump (160) is aligned vertically to coincide with the gap (310) separating the conductive bond pad (235) from the topographical feature (305). The topographical feature (305) provides thickness enhancement of a non-conductive layer (240) disposed over the semiconductor die (140) and the conductive bond pad (235) and stress buffering.

Abstract translation: 形成靠近用于将焊料凸块（160）耦合到半导体管芯（140）的导电接合焊盘（235）的形貌特征（305）。 地形特征（305）通过间隙（310）与导电接合垫（235）分离。 在一个实施例中，形貌特征（305）形成在稍微超过焊料凸块（160）的周边的位置处，其中凸起（160）的边缘垂直对准，以与间隔（310）分离重合 来自所述形貌特征（305）的所述导电接合焊盘（235）。 形貌特征（305）提供设置在半导体管芯（140）和导电接合焊盘（235）之上的非导电层（240）的厚度增强和应力缓冲。

公开(公告)号：WO2007146757A2

公开(公告)日：2007-12-21

申请号：PCT/US2007/070661

申请日：2007-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  SAUTER, Wolfgang

Inventor： DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  SAUTER, Wolfgang

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In a first aspect, a method comprises depositing a first metal containing layer (16) into a trench structure, which contacts a metalized area (12) of a semiconductor structure (10). The method further includes patterning at least one opening in a resist to the first metal containing layer (16). The opening should be in alignment with the trench structure. At least a pad metal containing layer (20) is formed within the at least one opening (preferably by electroplating processes). The resist (18) and the first metal layer (16) underlying the resist (18) are then etched (with the second metal layer (20) acting as a mask, in embodiments). The method includes flowing solder material (22) within the trench and on pad metal containing layer (20) after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.

Abstract translation: 在第一方面，一种方法包括将第一含金属层（16）沉积到与半导体结构（10）的金属化区域（12）接触的沟槽结构中。 该方法还包括将抗蚀剂中的至少一个开口构图到第一含金属层（16）。 开口应与沟槽结构对齐。 在至少一个开口内（优选地，通过电镀工艺）形成至少一块垫金属层（20）。 然后在实施例中蚀刻抗蚀剂（18）和抗蚀剂（18）下面的第一金属层（16）（第二金属层（20）用作掩模）。 该方法包括在蚀刻工艺之后使沟槽内的焊料材料（22）和衬垫金属含有层（20）流动。 该结构是受控的崩溃芯片连接（C4）结构，包括至少一个以抗蚀剂图形形成的电镀金属层，以形成至少一个球限制冶金层。 该结构还包括没有底切的底层金属层。

公开(公告)号：WO2005048304A2

公开(公告)日：2005-05-26

申请号：PCT/US2004/036660

申请日：2004-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BADAMI, Dinesh, A. ,  LEE, Tom, C. ,  LI, Baozhen ,  MATUSIEWICZ, Gerald ,  MOTSIFF, William, T. ,  MUZZY, Christopher, D. ,  WATSON, Kimball, M. ,  WYNNE, Jean, E.

Inventor： BADAMI, Dinesh, A. ,  LEE, Tom, C. ,  LI, Baozhen ,  MATUSIEWICZ, Gerald ,  MOTSIFF, William, T. ,  MUZZY, Christopher, D. ,  WATSON, Kimball, M. ,  WYNNE, Jean, E.

IPC: H01L

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract translation: 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝链接在第一介电层的顶部上。 熔丝链路电连接两个通孔并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方并直接位于两个过孔上方。 两个台面均包括第三自钝化导电材料。 激光熔丝通过将激光束引导至熔丝链路进行编程。 控制激光束使得响应于激光束对熔丝链路的影响，熔丝链路的电阻改变但熔丝链路不被熔断。 这种电阻变化被感测并转换成数字信号。