公开(公告)号：EP1953870A4

公开(公告)日：2012-07-11

申请号：EP06823175

申请日：2006-11-08

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： OKUDA YASUHIRO ,  HOSOE AKIHISA ,  FUJITA TARO

IPC: H01R11/01 ,  H01B5/16 ,  H01B13/00 ,  H01R43/00

CPC classification number: H01R13/03 ,  H01R4/04 ,  H01R11/01 ,  H01R43/0235 ,  H01R43/0249 ,  H01R43/0256 ,  H05K3/0035 ,  H05K3/326 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0156 ,  Y10T29/49204

公开(公告)号：EP2442627A1

公开(公告)日：2012-04-18

申请号：EP10187779.3

申请日：2010-10-15

Applicant: Odelo GmbH

Inventor： Barthel, Frank

IPC: H05K1/02 ,  H05K7/20 ,  H05K5/00 ,  F21S8/00

CPC classification number: H05K1/0201 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/09509 ,  H05K2201/09972 ,  H05K2201/10106

Abstract: Es wird eine Kraftfahrzeugleuchte mit einem durch ein Leuchtengehäuse (01) und eine dieses abschließende Lichtscheibe umschlossenen Leuchteninnenraum (02) beschrieben. Der Leuchteninnenraum beherbergt zumindest einen Leuchtmittelträger (01) mit Leiterbahnen (03). Auf dem zumindest einen Leuchtmittelträger (01) ist zusätzlich zu mindestens einer LED (07) mindestens ein weiteres Elektronikbauelement (05) angeordnet und elektrisch kontaktiert. Die Elektronikbauelemente (06, 02, 05, 07) sind nach wärmeempfindlichen Bauelementen (02), zu denen wenigstens die mindestens eine LED (07) zählt, und nach Leistungsbauelementen (05) unterschieden. Wenigstens eine in einem Leuchtmittelträger (01) angeordnete Wärmebresche (04) ist zumindest zwischen einem Leistungsbauelement (05) und einem wärmeempfindlichen Bauelement (02) angeordnet.

Abstract translation: 机动车灯具有包括与挡板（03）电连接的热敏部件（02），功率部件（05），电子模块（06）和LED（07）的灯座（01）。 形成热隙（04）以将灯座分成热区（08）和冷区（09）。 热敏部件和LED设置在冷部中，并且功率部件和电子模块设置在热部分中。

公开(公告)号：EP1796445A3

公开(公告)日：2011-09-14

申请号：EP07002566.3

申请日：1997-06-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H01L23/498 ,  H01L23/538

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprising a core substrate, multilayer wiring layers formed on the substrate by alternately laminating an interlaminar insulating layer and conductor pattern and a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers, characterized in that first, the solder pads located from first row to fifth row from an outer position of the solder pad group are constructed with flat pads connected to conductor patterns located on the outermost surface and having solder bumps formed on surfaces of the pads, while the solder pad group other than these solder pads are constructed with viaholes connected to a flat innerlayer pad group located in an inner layer and having solder bumps formed in recess portions of the viaholes and, second, the solder pads located from first row to fifth row from an outer position of the innerlayer pad group are constructed with flat pads connected to conductor patterns in the same layer as the innerlayer pad group, while the innerlayer pad group other than these pads are constituted with flat pads connected to a further innerlayer flat pad group located inward the above innerlayer through viaholes and, third, the layer having the structure of the above second feature is at least one layer.

公开(公告)号：EP2170028A4

公开(公告)日：2011-07-20

申请号：EP07790573

申请日：2007-07-10

Applicant: IBIDEN CO LTD

Inventor： TAKAHASHI MICHIMASA

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096

公开(公告)号：EP1659841B1

公开(公告)日：2011-03-16

申请号：EP06003039.2

申请日：1999-07-07

Applicant: IBIDEN CO., LTD.

Inventor： Tsukada, Kiyotaka ,  Takada, Masaru ,  Chihara, Kenji

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

公开(公告)号：EP2268112A1

公开(公告)日：2010-12-29

申请号：EP10186155.7

申请日：2006-10-24

Applicant: IBIDEN CO., LTD.

Inventor： The designation of the inventor has not yet been filed

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4644 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627

Abstract: A flexible substrate 13 having conductor patterns 132 and 133, and a non-flexible substrate 111 with rigidity are disposed adjacent to each other in the horizontal direction. The flexible substrate 13 and the non-flexibie substrate 111 are covered with insulating layers 111 and 113 so that at least a portion of the flexible substrate is exposed. Vias 116 and 141 are formed in the insulating layers 111 and 116 so as to reach the conductor patterns 132 and 133 of the flexible substrate 13, and wirings 117 and 142 are formed by plating to reach the conductor patterns 132 and 133 through the vias 116 and 141. The insulating layers 114, 115, 144, and 145 are laminated on the insulating layers 111 and 113, and circuits 123 and 150 are formed for connection of wiring.

Abstract translation: 具有导体图案132和133的柔性基板13和具有刚性的非柔性基板111在水平方向上彼此相邻布置。 柔性基板13和非柔性基板111被绝缘层111和113覆盖，从而露出柔性基板的至少一部分。 通孔116和141形成在绝缘层111和116中以便到达柔性基板13的导体图案132和133，并且布线117和142通过电镀形成以通过通孔116到达导体图案132和133 绝缘层114,115,144和145层叠在绝缘层111和113上，并且形成电路123和150用于布线的连接。

公开(公告)号：EP1924130A3

公开(公告)日：2010-11-17

申请号：EP08151537.1

申请日：1999-11-17

Applicant: IBIDEN CO., LTD.

Inventor： Ito, Hitoshi ,  Iwata, Yoshiyuki ,  Kawade, Masanori ,  Yazu, Hajime ,  Hirose, Naohiro

IPC: H05K1/11 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

Abstract: A package substrate (231) incorporating a build-up substrate having at least one structure in which a conductor layer and interlayer resin insulating layer are alternately laminated such that a conductive connecting pin (110) for establishing the electrical connection with another substrate is secured to said build-up substrate. Said package substrate comprises a pad (16) for securing said conductive connecting pin (110), wherein said pad (16) is covered with an organic resin insulating layer (15) having an opening (18) and connected to an inner conductor layer through a via hole, and said conductive connecting pin (110) is secured to said pad exposed to the outside through the opening through a conductive adhesive agent (17) formed in the opening.

公开(公告)号：EP1951016A4

公开(公告)日：2010-06-02

申请号：EP06822610

申请日：2006-10-30

Applicant: IBIDEN CO LTD

Inventor： TAKAHASHI MICHIMASA ,  AOYAMA MASAKAZU

IPC: H05K3/00 ,  H05K1/02 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096

公开(公告)号：EP1909546A4

公开(公告)日：2009-11-11

申请号：EP06766643

申请日：2006-06-13

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H05K1/11 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A printed wiring board includes a mounting portion 60 on which a dual core processor 80 including two processor cores 81A and 81B in a single chip can be mounted, power supply lines 12A and 12B, ground lines 11A and 11B, and a first layered capacitor 40A and a second layered capacitor 40B which are independently provided for each of the processor cores 81A and 81B, respectively. Accordingly, even when the electric potentials of the processor cores 81A and 81B instantaneously drop, an instantaneous drop of the electric potential can be suppressed by the action of the layered capacitors 40A and 40B corresponding to the processor cores 81A and 81B, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

Abstract translation: 印刷线路板包括：安装部分60，在该安装部分60上可以安装包括在单个芯片中的两个处理器芯81A和81B的双核处理器80;电源线12A和12B;接地线11A和11B;以及第一层状电容器40A 以及分别为每个处理器核心81A和81B独立提供的第二分层电容器40B。 因此，即使处理器芯81A和81B的电位瞬间下降，也能够通过分别与处理器芯81A和81B对应的分层电容器40A和40B的作用来抑制电位的瞬时下降。 另外，即使其中一个处理器内核的电压变化，电压的变化也不会影响另一个处理器内核，因此不会发生故障。

公开(公告)号：EP1923489A3

公开(公告)日：2009-05-27

申请号：EP08152454.8

申请日：1999-09-14

Applicant: Ibiden Co., Ltd.

Inventor： En, Honchin ,  Nakai, Tohru ,  Oki, Takeo ,  Hirose, Naohiro ,  Noda, Kouta

IPC: H05K3/18 ,  H05K3/46 ,  H05K1/09 ,  C25D5/18 ,  C23C18/34

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A multilayer printed circuit board (5010) comprises a core board (5030) and, as constructed on both sides thereof, a buildup wiring layer obtainable by building up an interlayer resin insulating layer (5050, 5150) and a conductor layer (5058, 5158) alternately with said conductor layers (5058, 5158) being interconnected by via holes (5160). The via holes (5060, 5160) are formed immediately over plated-through holes (5036) in the manner of plugging the through holes (5016) in the core board (5030). In a process for manufacturing the multilayer printed circuit board (5010), the through holes (5016) are pierced by laser light to be not larger than 200 µm in diameter.