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    REMOTE TEST FACILITY WITH WIRELESS INTERFACE TO LOCAL TEST FACILITIES
    26.
    发明公开
    REMOTE TEST FACILITY WITH WIRELESS INTERFACE TO LOCAL TEST FACILITIES 审中-公开
    与无线接口至本地测试设备的远程测试仪

    公开(公告)号：EP1836504A2

    公开(公告)日：2007-09-26

    申请号：EP05854353.9

    申请日：2005-12-15

    Applicant: FormFactor, Inc.

    Inventor： KHANDROS, Igor, Y. ,  ELDRIDGE, Benjamin, N.

    IPC: G01R31/26

    CPC classification number: G01R31/2884 ,  G01R31/3025 ,  G01R31/31907

    Abstract: A central test facility transmits wirelessly test data to a local test facility, which tests electronic devices using the test data. The local test facility transmits wirelessly response data generated by the electronic devices back to the central test facility, which analyzes the response data to determine which electronic devices passed the testing. The central test facility may provide the results of the testing to other entities, such as a design facility where the electronic devices were designed or a manufacturing facility where the electronic devices where manufactured. The central test facility may accept requests for test resources from any of a number of local test facilities, schedule test times corresponding to each test request, and at a scheduled test time, wirelessly transmits test data to a corresponding local test facility.

    TEST METHOD AND ASSEMBLY INCLUDING A TEST DIE FOR TESTING A SEMICONDUCTOR PRODUCT DIE
    30.
    发明公开
    TEST METHOD AND ASSEMBLY INCLUDING A TEST DIE FOR TESTING A SEMICONDUCTOR PRODUCT DIE 审中-公开
    试验方法和建设与芯片测试用于测试半导体芯片PRODUC

    公开(公告)号：EP1141735A2

    公开(公告)日：2001-10-10

    申请号：EP99968547.2

    申请日：1999-12-22

    Applicant: FORMFACTOR, INC.

    Inventor： ELDRIDGE, Benjamin, N. ,  KHANDROS, Igor, Y. ,  PEDERSEN, David, V. ,  WHITTEN, Ralph, G.

    IPC: G01R31/316

    CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A test assembly (2000) for testing product circuitry (202, 302, 304) of a product die (2011, 300). In one embodiment, the test assembly includes a test die (2010, 400) and an interconnection substrate (2008) for electrically coupling the test die to a host controller (2002) that communicates with the test die. The test die may be designed according to a design methodology (100) for a test die and a product die that includes the step of concurrently designing test circuitry (202A, 402, 404) and product circuitry in a unified design (102). The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions (104) the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product die may contain some test circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.

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