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    MICROSTRIP ARRANGEMENT
    22.
    发明公开
    MICROSTRIP ARRANGEMENT 审中-公开
    微带安排

    公开(公告)号：EP1032957A2

    公开(公告)日：2000-09-06

    申请号：EP98956084.2

    申请日：1998-11-19

    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (publ)

    Inventor： BERGSTEDT, Leif ,  GEORGIAN, Spartak

    IPC: H01P3/08 ,  H01Q13/20

    CPC classification number: H01P3/084 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q13/206 ,  H01Q21/0081 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2201/09972

    Abstract: The invention relates to a microstrip arrangement comprising a first and a second microstrip conductor. The two microstrip conductors have essentially the same dimensions in their longitudinal direction and transverse direction, and are galvanically interconnected by means of at least one connection. The two microstrip conductors also extend essentially parallel to one another on either side of a dielectric material. As a result of this design of the microstrip arrangement, the field losses and also other influences caused by the dielectric material will be very considerably reduced, and in practice a resultant microstrip arrangement is obtained, which, with regard to its electrical performance, appears to be suspended in the air. Preferred embodiments comprise a microstrip antenna, a circuit board and a conductor application.

    Abstract translation: 本发明涉及包括第一和第二微带导体的微带装置。 两个微带导体在其纵向方向和横向方向上具有基本相同的尺寸，并且通过至少一个连接电流互连。 两个微带导体也在电介质材料的任一侧基本上彼此平行地延伸。 由于微带装置的这种设计，由介电材料引起的场损耗和其它影响将非常显着地降低，并且实际上获得了所得到的微带结构，就其电性能而言，似乎 悬浮在空中。 优选实施例包括微带天线，电路板和导体应用。

    PRINTED CIRCUIT BOARD LAYERING CONFIGURATION FOR VERY HIGH BANDWIDTH INTERCONNECT
    23.
    发明公开
    PRINTED CIRCUIT BOARD LAYERING CONFIGURATION FOR VERY HIGH BANDWIDTH INTERCONNECT 失效
    对层构造与非常高的带宽连接电路板

    公开(公告)号：EP0914688A4

    公开(公告)日：2000-01-05

    申请号：EP97933340

    申请日：1997-07-07

    Applicant: STORAGE TECHNOLOGY CORP

    Inventor： HAMRE JOHN D

    IPC: H05K1/11 ,  H01P1/04 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/36 ,  H01P5/02

    CPC classification number: H01P1/047 ,  H05K1/0219 ,  H05K3/361 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2201/09354 ,  H05K2201/09618 ,  H05K2201/0979

    Abstract: A ground plane interconnection is provided on first and second substrates (100, 112), the first and second substrates (100, 112) having respective first and second ground layers (110, 118) disposed on a first surface of each of the first and second substrates (100, 112). A ground conductor strip (120) is disposed on a second surface of the second substrate (112), wherein the ground conductor strip (120) includes a plurality of electrically conductive members (124) which pass through the second substrate (112) to electrically couple the ground conductor strip (120) and the second ground layer (118). The first substrate (100) is positioned with respect to the second substrate (112) such that when the first substrate (100) is placed proximate the second substrate (112), the ground conductor strip (120) electrically couples the first and second ground layers (110, 118) to form a continuous ground plane. A method of forming a reduced-inductance continuous ground plane is also provided.

    PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME
    24.
    发明公开
    PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME 失效
    VEDFAHREN ZU DEREN HERSTELLUNG的GEDRUCKTE SCHALTUNGSPLATTE

    公开(公告)号：EP0817548A4

    公开(公告)日：1999-12-01

    申请号：EP96942586

    申请日：1996-12-19

    Applicant: IBIDEN CO LTD

    Inventor： MORI YOJI ,  KAWAMURA YOICHIRO

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46

    CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

    Abstract: A printed wiring board (1) such that openings (8L) formed around a pad (12L) which is a photo-via land do not overlap a pad (12L) and the area of each of the openings (8L) around the pad (12L) is equal to that of each of the other openings (8), the amount of resin (13) with which each of the openings (8, 8L) is filled is equal to that with which each of the openings (8L) is filled over the whole wiring board (1), and the amounts of resin (13) overflowing from the openings (8, 8L) are equal to each other. The circuit pattern provided on the upper surface of an interlayer insulating layer formed on the printed wiring board can be connected to a conductor pad area without causing any defective connection, providing a highly-reliable printed wiring board.

    Abstract translation: 印刷电路板，其中存在于作为光电二极管的焊盘周围的开口布置成使其不与焊盘重叠，存在于焊盘周围的开口的面积和另一个开口的面积相等，树脂的量 填充在每个开口中或在整个印刷线路板上均匀化，并且设置从每个开口溢出的树脂量或当树脂在每个开口中填充或均匀时。 根据这样的印刷电路板，当通过布置开口来连接设置在形成在印刷线路板上的层间绝缘板上的电路图案和导体焊盘时，可以实现其中安全连接不会导致断开的可靠的印刷线路板 存在于导体焊盘周围，使得其不与导体焊盘重叠，并且基本上均匀地填充在导体焊盘周围的开口中的树脂的量和填充在另一个开口中的树脂的量。

    Redundant multitier contacts for a solid state x-ray detector
    25.
    发明公开
    Redundant multitier contacts for a solid state x-ray detector 有权
    用于固态X射线探测器的冗余多层触点

    公开(公告)号：EP0924774A3

    公开(公告)日：1999-11-10

    申请号：EP98310178.3

    申请日：1998-12-11

    Applicant: GENERAL ELECTRIC COMPANY

    Inventor： Vafi, Habib ,  Petrick, Scott William ,  Allen, Philip Marshall ,  Saunders, Rowland Frederick

    IPC: H01L31/02 ,  H01L27/146

    CPC classification number: H01L31/02002 ,  H05K1/117 ,  H05K3/225 ,  H05K3/361 ,  H05K2201/0979

    Abstract: A connection method for connecting scan and data or row and column drive components applies redundant multitier contacts on the components. Multitier redundant sets of contacts (12) are deposited on a fine pitch component (10), such as an X-ray detector intended to be connected to associated electronics (14). A flexible circuit (18) is then bonded to a first one of the multitier sets of contacts (12) on the fine pitch component (10), the flexible circuit (18) forming a permanent connection to the associated electronics (14). Multitier redundant sets of contacts (16) can also be deposited on the associated electronics (14). Then defect free portions of solid state X-ray detector connections can be salvaged in instances where the bonding process produces a poor connection in an isolated area, or the detector and/or associated electronics can be salvaged if either the detector or part of the associated electronics are defective.

    Abstract translation: 用于连接扫描和数据或行和列驱动器组件的连接方法在组件上应用冗余多层触点。 在精细间距部件（10）（例如旨在连接到相关电子设备（14）的X射线检测器）上沉积多层冗余触点组（12）。 然后将挠性电路（18）接合到细间距部件（10）上的多层触点组（12）中的第一组触点（12），挠性电路（18）与相关联的电子部件（14）形成永久连接。 也可以在相关的电子器件（14）上沉积多重冗余的触点组（16）。 然后，在结合过程在隔离区域中产生不良连接的情况下，可以挽救固态X射线检测器连接的无缺陷部分，或者如果检测器或相关联的部分中的任一个可以回收检测器和/ 电子产品有缺陷。

    Multilayer interconnection substrate
    27.
    发明公开
    Multilayer interconnection substrate 失效
    Mehrschichtiges Verbindungssubstrat。

    公开(公告)号：EP0457583A2

    公开(公告)日：1991-11-21

    申请号：EP91304397.2

    申请日：1991-05-16

    Applicant: NEC CORPORATION

    Inventor： Hasegawa, Shinichi

    IPC: H01L23/538

    CPC classification number: H01L23/538 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/115 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

    Abstract: First to third power interconnections are provided by first to third interconnection layers (56, 57, 42). A first insulating layer (54) is provided between the first and second interconnection layers (56, 57), and a second insulating layer (55) is provided between the second and third interconnection layers (57, 42). A plurality of first via holes (41) are provided in the first insulating layer (54) and connect the first and second power interconnection layers (56, 57), and a plurality of second via holes (43) are provided in the second insulating layer (55) with positions shifted from those of the first via holes (41) and connect the second and third power interconnection layers (57, 42). A ceramic or glass ceramic substrate (50) supports the layers (54, 56, 57, 55, 42). The structure has lower distribution resistance.

    Abstract translation: 第一至第三互连层由第一至第三互连层（56,57,42）提供。 第一绝缘层（54）设置在第一和第二互连层（56,57）之间，第二绝缘层（55）设置在第二和第三互连层（57,42）之间。 多个第一通孔（41）设置在第一绝缘层（54）中并且连接第一和第二电力互连层（56,57），并且多个第二通孔（43）设置在第二绝缘层 层（55），其位置偏离第一通孔（41）的位置，并连接第二和第三电力互连层（57,42）。 陶瓷或玻璃陶瓷基板（50）支撑层（54,56,57,55,42）。 该结构具有较低的分布阻力。

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