公开(公告)号：EP3216058A1

公开(公告)日：2017-09-13

申请号：EP15856210.8

申请日：2015-11-04

申请人： Texas Instruments Incorporated

发明人： EUGENE LEE, Lee Han Meng ,  BIN ABDUL AZIZ, Anis Fauzi ,  FEN, Sueann Lim Wei

IPC分类号： H01L27/085

CPC分类号： H01L25/50 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/34 ,  H01L24/37 ,  H01L24/38 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L25/071 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

摘要翻译： 一种用于形成堆叠式半导体封装的方法包括提供包括倒置的LF的底部引线框架（LF）面板，每个LF包括至少多个端子。 低侧（LS）晶体管连接到第一管芯附着区域。 包括倒置并互连的第一夹子的第一夹子面板放置在底部LF面板上。 介质插入器连接在LS晶体管上的第一个夹子上。 高端（HS）晶体管连接在插入器上。 包括多个第二夹子的第二夹子面板配合以互连至HS晶体管，包括将第二夹子面板，第一夹子面板和底部LF面板配合在一起。 LF可以包括第二管芯附着区域和附着在第二管芯附着区域上的控制器管芯，然后将控制器管芯的焊盘引线键合到多个端子。

公开(公告)号：EP2693474A2

公开(公告)日：2014-02-05

申请号：EP13177989.4

申请日：2013-07-25

申请人： IXYS CORPORATION

发明人： Zommer, Nathan

IPC分类号： H01L23/485 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L23/48 ,  H01L23/3735 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/80 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/95 ,  H01L2224/03312 ,  H01L2224/0345 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0381 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05687 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/0589 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/08238 ,  H01L2224/4007 ,  H01L2224/40225 ,  H01L2224/40247 ,  H01L2224/40475 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73221 ,  H01L2224/73251 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/80439 ,  H01L2224/80895 ,  H01L2224/84205 ,  H01L2224/84424 ,  H01L2224/84801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/92 ,  H01L2224/92157 ,  H01L2224/9222 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/05432 ,  H01L2224/05139 ,  H01L2924/00015 ,  H01L2224/80 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/08 ,  H01L2224/40 ,  H01L2224/48 ,  H01L2224/03 ,  H01L2924/207 ,  H01L2224/37099

摘要： A method of manufacturing a semiconductor die, comprising the steps of: (a) forming a plurality of separate amounts of silver nanoparticle paste on a top- side of a wafer (26) such that there is an amount of silver nanoparticle paste on a first aluminum pad (28) and such that there is no silver nanoparticle paste (29) on a second aluminum pad (27); and (b) sintering the amount of silver nanoparticle paste so that the amount of silver nanoparticle paste becomes a sintered silver structure disposed on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver layer.

摘要翻译： （a）在晶片（26）检测的顶侧形成的银纳米粒子膏的单独量的多元化thatthere是银纳米粒子膏的量上的第一：制造半导体其中，包括以下步骤的方法 铝垫（28）和这样thatthere没有银纳米粒子膏（29）上的第二铝焊盘（27）; 和（b）烧结的银纳米粒子膏的量，从而没有银纳米粒子膏的量变得设置在所述第一铝垫（28）的烧结银结构，所以没有第二铝垫（27）未包括的任何烧结银 层。

公开(公告)号：EP3308396A1

公开(公告)日：2018-04-18

申请号：EP16807990.3

申请日：2016-05-11

申请人： Vishay General Semiconductor LLC

发明人： DING, Hui-Ying ,  WANG, Pengnian ,  YU, Tao ,  LIU, Jun-Feng ,  BAI, Jun-Kai ,  PENG, Chih-Ping

IPC分类号： H01L23/495 ,  H01L23/433 ,  H01L23/31 ,  H01L23/64 ,  H01L33/48

CPC分类号： H01L23/49575 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2021/6027 ,  H01L2021/60277 ,  H01L2224/04026 ,  H01L2224/05644 ,  H01L2224/291 ,  H01L2224/32145 ,  H01L2224/33 ,  H01L2224/33181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/37166 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83466 ,  H01L2224/83815 ,  H01L2224/84345 ,  H01L2224/84385 ,  H01L2224/92246 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor assembly includes a semiconductor die comprising lower and upper electrical contacts. A lead frame having a lower die pad is electrically and mechanically connected to the lower electrical contact of the die. An upper conductive member has a first portion electrically and mechanically connected to the upper electrical contact of the die. A lead terminal has a surface portion electrically and mechanically connected to a second portion of the conductive member. The surface portion of the lead terminal and/or the second portion of the conductive member has a series of grooves disposed therein. Packaging material encapsulates the semiconductor die, at least a portion of the lead frame, at least a portion of the upper conducive member and at least a portion of the lead terminal.

公开(公告)号：EP2846356A3

公开(公告)日：2015-08-26

申请号：EP14180144.9

申请日：2014-08-07

申请人： Renesas Electronics Corporation

发明人： Muto, Akira ,  Furukawa, Takafumi

IPC分类号： H01L25/11 ,  H01L25/18 ,  H01L23/495 ,  H02M7/00

CPC分类号： H01L25/072 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/115 ,  H01L25/162 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0635 ,  H01L29/739 ,  H01L29/7393 ,  H01L29/861 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02M7/003 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/00013 ,  H01L2924/0665

摘要： An improvement is achieved in the performance of an electronic device. A first semiconductor device and a second semiconductor device are mounted over the upper surface of a wiring board such that, e.g., in plan view, the orientation of the second semiconductor device intersects the orientation of the first semiconductor device. That is, the first semiconductor device is mounted over the upper surface of the wiring board such that a first emitter terminal and a first signal terminal are arranged along an x-direction in which the pair of shorter sides of the wiring board extend. On the other hand, the second semiconductor device is mounted over the upper surface of the wiring board such that a second emitter terminal and a second signal terminal are arranged along a y-direction in which the pair of longer sides of the wiring board extend.

公开(公告)号：EP3002782A1

公开(公告)日：2016-04-06

申请号：EP15184643.3

申请日：2015-09-10

申请人： Renesas Electronics Corporation

发明人： MUTO, Akira ,  BANDO, Koji ,  SATO, Yukihiro ,  MITAMURA, Kazuhiro

IPC分类号： H01L21/60 ,  H01L23/492 ,  H01L23/495 ,  H02M7/00

CPC分类号： H01L23/49575 ,  B60L3/003 ,  B60L11/1803 ,  B60L15/007 ,  B60L2220/12 ,  B60L2240/525 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49565 ,  H01L23/544 ,  H01L23/564 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29116 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40998 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/77704 ,  H01L2224/78704 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/84136 ,  H01L2224/84138 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/84862 ,  H01L2224/8585 ,  H01L2224/92147 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  Y02T10/645 ,  Y02T10/7005 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05559 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

摘要： The present invention is directed to a method for assembling a semiconductor device and the resulting device, wherein the method comprising the steps of:
a) Providing a lead frame (LF) that comprises a plurality of leads (LD1, LD2) and a pair of support parts (SPU).
b) Disposing the lead frame (LF) above a chip mounting part (TAB) on which the semiconductor chip (CHP1) and the semiconductor chip (CHP2) have been mounted.
c) Forming a conductive adhesive (ADH2) made of, for example, a silver paste or a high-melting-point solder on the anode electrode pads (ADP) of the semiconductor chips (CHP1, CHP2).
d) Providing a clip (CLP) having the main body part (BDU) and a pair of extension parts (EXU) on opposite sides of said main body part (BDU).
e) Mounting the clip (CLP) over the lead (LF) so that the clip (CLP) is supported by the pair of extension parts (EXU) and the main body part (BDU) at three different points.
By using this method a conductive adhesive (ADH2) with an even layer thickness can be obtained.
Thereby the thermal fatigue resistance of the semiconductor device can be improved.

摘要翻译： 本发明涉及一种用于组装半导体器件的方法和所得到的器件，其中该方法包括以下步骤：a）提供引线框架（LF），该引线框架包括多个引线（LD1，LD2）和一对 支持部件（SPU）。 b）将引线框架（LF）置于安装有半导体芯片（CHP1）和半导体芯片（CHP2）的芯片安装部分（TAB）上方。 c）在半导体芯片（CHP1，CHP2）的阳极电极垫（ADP）上形成由例如银膏或高熔点焊料制成的导电粘合剂（ADH2）。 d）在所述主体部分（BDU）的相对侧上提供具有主体部分（BDU）和一对延伸部分（EXU）的夹子（CLP）。 e）将夹子（CLP）安装在引线（LF）上方，使夹子（CLP）在一对延伸部件（EXU）和主体部件（BDU）的三个不同点上得到支撑。 通过使用这种方法，可以获得具有均匀层厚度的导电粘合剂（ADH2）。 由此可以提高半导体器件的耐热疲劳性。

公开(公告)号：EP2916348A4

公开(公告)日：2016-01-27

申请号：EP13851001

申请日：2013-10-25

申请人： NSK LTD

发明人： SUNAGA TAKASHI ,  KANEKO NOBORU ,  MIYOSHI OSAMU

IPC分类号： H01L21/60 ,  B62D5/04 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L23/49551 ,  B62D5/0406 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40159 ,  H01L2224/40225 ,  H01L2224/4103 ,  H01L2224/41175 ,  H01L2224/73263 ,  H01L2224/77272 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84095 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor module is provided for shortening a manufacturing tact time and reduce manufacturing costs and for ensuring reliability of a bonding portion. The semiconductor module includes a substrate (31) formed of a metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on one wiring pattern (33a) via a solder (34a), and copper connectors (36a, 36b) that connects electrodes (S, G) formed on the bear-chip transistor (35) and other wiring patterns (33b, 33c) via a solder (34b, 34c). The copper connectors (36a, 36b) has a bridge shape, has a width-reduced portion (36ag) formed in the vicinity of the bonding face (36af) to the electrodes (S, G), and has a stress-reducing portion (36ak) formed on the bonding face (36af) bonded to the electrode (S, G).

公开(公告)号：EP2521176B1

公开(公告)日：2014-06-11

申请号：EP12163619.5

申请日：2012-04-10

申请人： International Rectifier Corporation

发明人： Cheah, Chuan ,  Park, Dae Keun

IPC分类号： H01L25/18 ,  H01L23/495 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74

CPC分类号： H01L23/49844 ,  H01L21/56 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L25/074 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/06181 ,  H01L2224/32145 ,  H01L2224/37147 ,  H01L2224/40145 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15787 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00

公开(公告)号：EP2720263A1

公开(公告)日：2014-04-16

申请号：EP11867292.2

申请日：2011-06-09

申请人： Mitsubishi Electric Corporation

发明人： OGA Takuya ,  SAKAMOTO Kazuyasu ,  SUGIHARA Tsuyoshi ,  KATO Masaki ,  NAKASHIMA Daisuke ,  JIDA Tsuyoshi ,  TADA Gen

IPC分类号： H01L23/48 ,  H01L25/07 ,  H01L25/18 ,  H01L29/78

CPC分类号： H01L23/4952 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/115 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/29201 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40179 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83143 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84138 ,  H01L2224/84143 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2224/85205 ,  H01L2224/92157 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/83205 ,  H01L2224/37099

摘要： A semiconductor device is provided, in which a first lead (11) is joined with the bottom electrode (23) of a MOS-FET (21) with first solder (51), the top electrode (22) of the MOS-FET is joined with an internal lead (31) with second solder (52), the internal lead is joined with a projection (61) of a second lead with third solder (53), and the first lead, second lead, MOS-FET and internal lead are integrally molded using sealing resin (41), wherein the first solder and second solder include support members (54) and (55), respectively, located thereinside and positions of the internal lead and MOS-FET are stabilized by self-alignment.

摘要翻译： 提供一种半导体器件，其中第一引线（11）与第一焊料（51）与MOS-FET（21）的底电极（23）接合，MOS-FET的顶电极（22） 内引线与第二引线与第三焊料（53）的突起（61）连接，并且第一引线，第二引线，MOS-FET和内部引线 引线是用密封树脂（41）整体模制的，其中第一焊料和第二焊料分别包括位于其内部的支撑部件（54）和（55），并且内部引线和MOS-FET的位置通过自对准而稳定。

公开(公告)号：EP3355350A1

公开(公告)日：2018-08-01

申请号：EP18150713.8

申请日：2018-01-09

申请人： Renesas Electronics Corporation

发明人： NAKAMURA, Hiroyuki ,  SHIMOYAMA, Hiroya

IPC分类号： H01L23/495 ,  H01L25/16 ,  B62D5/04

CPC分类号： H01L23/49575 ,  B62D5/0406 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L27/0629 ,  H01L29/66992 ,  H01L29/78 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/09165 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/40499 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/49179 ,  H01L2224/49505 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/84801 ,  H01L2224/84862 ,  H01L2224/85013 ,  H01L2224/92246 ,  H01L2224/92247 ,  H02M7/003 ,  H02M7/537 ,  H02P27/06 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/01047

摘要： The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

公开(公告)号：EP3216058A4

公开(公告)日：2018-07-04

申请号：EP15856210

申请日：2015-11-04

申请人： TEXAS INSTRUMENTS INC

发明人： EUGENE LEE LEE HAN MENG ,  BIN ABDUL AZIZ ANIS FAUZI ,  FEN SUEANN LIM WEI

IPC分类号： H01L27/085 ,  H01L23/495

CPC分类号： H01L25/50 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/34 ,  H01L24/37 ,  H01L24/38 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L25/071 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.