公开(公告)号：US20170131476A1

公开(公告)日：2017-05-11

申请号：US14933668

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Eric Turcotte ,  Thomas E. Lombardi

IPC: G02B6/30 ,  G02B6/13

CPC classification number: G02B6/30 ,  G02B6/13 ,  G02B6/4239 ,  G02B6/4243 ,  G02B6/428

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

公开(公告)号：US20160043048A1

公开(公告)日：2016-02-11

申请号：US14886177

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03845 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/11011 ,  H01L2224/1134 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/2064

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.

公开(公告)号：US20160027744A1

公开(公告)日：2016-01-28

申请号：US14876889

申请日：2015-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03

Abstract: A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract translation: 一种方法，包括在导电焊盘上方和金属结构之上形成第一电介质层，导电焊盘和金属结构各自位于衬底上方的互连层内，在第一介电层中形成第一开口和第二开口， 所述第一开口与所述导电焊盘对准并且暴露所述导电焊盘，并且所述第二开口与所述金属结构对准并且暴露所述金属结构，并且在所述导电焊盘上，所述金属结构上以及所述第一介电层上方形成金属衬垫。 该方法还可以包括在金属衬垫之上形成第二电介质层，以及在第二电介质层之上形成第三电介质层，第三电介质层比第一电介质层或第二电介质层厚。

公开(公告)号：US20170148754A1

公开(公告)日：2017-05-25

申请号：US15421737

申请日：2017-02-01

Applicant: GlobalFoundries Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US09633962B2

公开(公告)日：2017-04-25

申请号：US14048483

申请日：2013-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L21/7684 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/014

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

公开(公告)号：US09466547B1

公开(公告)日：2016-10-11

申请号：US14734600

申请日：2015-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/54

CPC classification number: H01L23/3171 ,  H01L21/4853 ,  H01L21/563 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/03

Abstract: A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

Abstract translation: 在集成电路（IC）芯片钝化层内形成一种形貌结构。 形貌结构包括在钝化层的顶表面下方延伸的沟槽，并且在与IC芯片的最上面布线相关联的钝化层下面的最上面的金属间介电层的顶表面之上。 形貌结构还可以包括沿着沟槽的周边的钝化层的顶表面上方的脊。 形状结构可以位于一系列IC芯片接触焊盘之间和/或可以位于特定的IC芯片接触焊盘周围。 形貌结构增加了钝化层的表面积，从而增加了与钝化层的底部填充结合。 地形结构还影响毛细管底部填充物的毛细管运动，并且可以定位成加速，减慢或转移毛细管底部填充物的移动。

公开(公告)号：US10714411B2

公开(公告)日：2020-07-14

申请号：US15921852

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC: H01L23/48 ,  H01L23/488 ,  H01L25/065

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US10409006B2

公开(公告)日：2019-09-10

申请号：US15874210

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Charles L. Arvin ,  Robert Leidy

IPC: G02B6/12 ,  G02B6/34 ,  G02B6/30 ,  G02B6/124 ,  G02B6/13 ,  G02B6/36

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

公开(公告)号：US09933577B2

公开(公告)日：2018-04-03

申请号：US15068059

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffery P. Gambino ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Charles L. Arvin ,  Robert Leidy

IPC: G02B6/12 ,  G02B6/34 ,  G02B6/30 ,  G02B6/124 ,  G02B6/13

CPC classification number: G02B6/34 ,  G02B6/124 ,  G02B6/13 ,  G02B6/30

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

公开(公告)号：US09331037B2

公开(公告)日：2016-05-03

申请号：US14886177

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03845 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/11011 ,  H01L2224/1134 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/2064

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.

Abstract translation: “粗线模具”，在制造过程中，避免在“不连续”的顶部定位光致抗蚀剂层（例如，干膜光致抗蚀剂层的边缘）的直立边缘。这样焊料不会流入机械 光致抗蚀剂层和光致抗蚀剂层下面的层之间在光致抗蚀剂层的直立边缘附近的界面。