Patent search ap:("INTEL CORPORATION") AND inv:"Thorsten MEYER" Page 1

1.

发明申请
MICROELECTRONIC PACKAGE HAVING A PASSIVE MICROELECTRONIC DEVICE DISPOSED WITHIN A PACKAGE BODY 审中-公开

公开(公告)号：US20180286799A1

公开(公告)日：2018-10-04

申请号：US15997555

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Thorsten MEYER , Gerald OFNER , Andreas WOLTER , Georg SEIDEMANN , Sven ALBERS , Christian GEISSLER

IPC: H01L23/498 , H01L21/48 , H01L21/56

CPC classification number: H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L23/49822 , H01L23/50 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/16 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/24195 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/15151 , H01L2924/15159 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

2.

发明申请
OPOSSUM-DIE PACKAGE-ON-PACKAGE APPARATUS 审中-公开
Title translation: OPUMUM-DIE PACKAGE-ON-PACKAGE APPARATUS

公开(公告)号：US20160358891A1

公开(公告)日：2016-12-08

申请号：US14778018

申请日：2014-12-15

Applicant: INTEL CORPORATION

Inventor： Christian GEISSLER , Thorsten MEYER

IPC: H01L25/065 , H01L25/00

Abstract: An apparatus including a first package coupled to a second package, wherein each of the first package and the second package has a first side and an opposite second side; a first die coupled to the first package; and a second die coupled to the second side of the second package, wherein the first package is coupled to the second package in a stacked arrangement such that the first side of the second package faces the second side of the first package. A method including coupling a first package to a second package in a stacked configuration, wherein the first package includes a first package substrate and a first die and the second package includes a second package substrate and a second die, wherein the second die is disposed on a side of the second package substrate opposite the first package substrate.

Abstract translation: 一种包括耦合到第二封装的第一封装的装置，其中所述第一封装和所述第二封装中的每一个具有第一侧和相对的第二侧; 耦合到所述第一封装的第一管芯; 以及耦合到所述第二封装的第二侧的第二裸片，其中所述第一封装以堆叠布置耦合到所述第二封装，使得所述第二封装的所述第一侧面向所述第一封装的第二侧。一种包括以堆叠结构将第一封装耦合到第二封装的方法，其中所述第一封装包括第一封装衬底和第一管芯，所述第二封装包括第二封装衬底和第二管芯，其中所述第二管芯设置在所述第二封装基板的与所述第一封装基板相对的一侧。

3.

发明申请
THREE DIMENSIONAL STRUCTURES WITHIN MOLD COMPOUND 有权
Title translation: 模具化合物中的三维结构

公开(公告)号：US20160358897A1

公开(公告)日：2016-12-08

申请号：US14778036

申请日：2014-12-09

Applicant: INTEL CORPORATION

Inventor： Sven ALBERS , Andreas WOLTER , Klaus REINGRUBER , Thorsten MEYER

IPC: H01L25/16 , H01L23/31 , H01L21/56 , H01L23/498 , H01L49/02 , H01L21/683

CPC classification number: H01L25/16 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/48 , H01L23/49816 , H01L23/552 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/92 , H01L24/96 , H01L25/065 , H01L25/0655 , H01L25/07 , H01L25/50 , H01L28/00 , H01L2221/68359 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81201 , H01L2224/81815 , H01L2224/92125 , H01L2924/15311 , H01L2924/15313 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H01L2924/014 , H01L2924/00014

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

Abstract translation: 一种方法，包括通过积聚过程在衬底上形成至少一个被动结构; 在衬底上引入一个或多个集成电路芯片; 以及在所述至少一个无源结构和所述一个或多个集成电路芯片上引入模塑料。一种方法，包括通过三维印刷方法在基板上形成至少一个被动结构; 在衬底上引入一个或多个集成电路芯片; 以及将所述至少一个被动结构和所述一个或多个集成电路芯片嵌入到模塑料中。一种包括包括至少一个三维印刷无源结构和嵌入在成型材料中的一个或多个集成电路芯片的封装基板的装置。

4.

发明申请
METHOD OF EMBEDDING WLCSP COMPONENTS IN E-WLB AND E-PLB 审中-公开

公开(公告)号：US20180269190A1

公开(公告)日：2018-09-20

申请号：US15982787

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Vijay K. NAIR , Thorsten MEYER

IPC: H01L25/16 , H01L23/00 , H01L21/56

CPC classification number: H01L25/162 , H01L21/568 , H01L23/5389 , H01L24/05 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/03 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/05571 , H01L2224/05611 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/16505 , H01L2224/24137 , H01L2224/24195 , H01L2224/48227 , H01L2224/96 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/141 , H01L2924/1421 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/15331 , H01L2924/19011 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/3651 , H01L2224/81

Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.

5.

发明申请
MULTI-LAYER PACKAGE 审中-公开

公开(公告)号：US20170207170A1

公开(公告)日：2017-07-20

申请号：US15106761

申请日：2015-07-22

Applicant: INTEL CORPORATION

Inventor： Vijay K. NAIR , Chuan HU , Thorsten MEYER

IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31

Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.

6.

发明申请
RADIO DIE PACKAGE WITH BACKSIDE CONDUCTIVE PLATE 审中-公开
Title translation: 带背面导电板的无线电套件

公开(公告)号：US20170062357A1

公开(公告)日：2017-03-02

申请号：US14909939

申请日：2015-03-19

Applicant: Intel Corporation

Inventor： Teleshpor KAMGAING , Thorsten MEYER

IPC: H01L23/00 , H01L23/552 , H01L23/66 , H01Q1/38 , H01L21/48 , H01L21/56 , H01Q1/22 , H01Q1/24 , H01L23/373 , H01L25/065

CPC classification number: H01L23/562 , H01L21/485 , H01L21/4853 , H01L21/4882 , H01L21/565 , H01L23/36 , H01L23/373 , H01L23/49816 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/19 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/105 , H01L2223/6616 , H01L2223/6672 , H01L2223/6677 , H01L2224/02372 , H01L2224/02379 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/16235 , H01L2224/24137 , H01L2224/24195 , H01L2224/24245 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82047 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/92244 , H01L2225/06513 , H01L2225/06537 , H01L2225/06548 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/10253 , H01L2924/1421 , H01L2924/1434 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/3511 , H01Q1/2283 , H01Q1/241 , H01Q1/38

Abstract: A package is described for a radio frequency die that has a backside conductive plate. One example includes a conductive plate, a semiconductor die having a front side and a back side, the back side being attached to the plate, a radio frequency component attached to the plate, a dielectric filled cavity in the plate adjacent to the radio frequency component, and a redistribution layer attached to the front side of the die for external connection.

Abstract translation: 描述了一种具有背面导电板的射频管芯的封装。一个例子包括导电板，具有前侧和后侧的半导体管芯，其背面附接到板上，附接到板的射频部件，邻近射频部件的板中的电介质填充腔，以及连接到模具前侧的再分配层，用于外部连接。

7.

发明申请
METHOD OF EMBEDDING WLCSP COMPONENTS IN E-WLB AND E-PLB 有权
Title translation: 嵌入WLCSP组件在E-WLB和E-PLB中的方法

公开(公告)号：US20160276325A1

公开(公告)日：2016-09-22

申请号：US14767902

申请日：2014-09-18

Applicant: INTEL CORPORATION

Inventor： Vijay K. NAIR , Thorsten MEYER

IPC: H01L25/16 , H01L21/56 , H01L25/00 , H01L23/00

CPC classification number: H01L25/162 , H01L21/568 , H01L23/5389 , H01L24/05 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/03 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/05571 , H01L2224/05611 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/16505 , H01L2224/24137 , H01L2224/24195 , H01L2224/48227 , H01L2224/96 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/141 , H01L2924/1421 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/15331 , H01L2924/19011 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/3651 , H01L2924/00014 , H01L2224/81

Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.

Abstract translation: 本发明的实施例包括多管芯封装和制造这种多管芯封装的方法。在一个实施例中，模具层具有与第一表面相对的第一表面和第二表面。一个或多个第一电气部件，其每个具有被定向成面向模具层的第一表面的可焊接端子。模具层还可以具有一个或多个第二电气部件，每个第二电气部件具有定向成面向模具层的第二表面的第二类型的端子。实施例还可以包括在模具层的第一表面和模具层的第二表面之间形成的一个或多个导电通孔。因此，可以从模具层的第二表面到面向模具层的第一表面的第一电气部件进行电连接。