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公开(公告)号：US11031347B2
公开(公告)日：2021-06-08
申请号：US16381319
申请日：2019-04-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-lyong Kim , Hyun-soo Chung , Dong-hyeon Jang
IPC: H01L23/552 , H01L23/538 , H01L23/00 , H01L23/34 , H01L23/367 , H01L23/433 , H01L25/065 , H01L25/10 , H01L23/498
Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.
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Patent Agency Ranking
公开(公告)号：US10438899B2
公开(公告)日：2019-10-08
申请号：US15869517
申请日：2018-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-lyong Kim , Hyun-soo Chung , Dong-hyeon Jang
IPC: H01L23/552 , H01L23/538 , H01L23/00 , H01L23/34 , H01L23/367 , H01L23/433 , H01L25/065 , H01L25/10
Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.
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公开(公告)号：US20190237410A1
公开(公告)日：2019-08-01
申请号：US16381319
申请日：2019-04-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-lyong KIM , Hyun-soo Chung , Dong-hyeon Jang
IPC: H01L23/552 , H01L23/00 , H01L23/34 , H01L23/538 , H01L23/367 , H01L23/433
CPC classification number: H01L23/552 , H01L23/345 , H01L23/367 , H01L23/4334 , H01L23/5384 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/12105 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32145 , H01L2224/32245 , H01L2224/48227 , H01L2224/73204 , H01L2224/73267 , H01L2224/83851 , H01L2224/83862 , H01L2224/83874 , H01L2224/92244 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/3025 , H01L2924/3511 , H01L2224/83 , H01L2924/0665 , H01L2924/069 , H01L2924/0635
Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.
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公开(公告)号：US09136260B2
公开(公告)日：2015-09-15
申请号：US14093853
申请日：2013-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
IPC: H01L25/00 , H01L23/48 , H01L21/56 , H01L23/00 , H01L25/065 , H01L21/768 , H01L21/683 , H01L25/18
CPC classification number: H01L25/50 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/3192 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2221/68381 , H01L2224/0346 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11009 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/2929 , H01L2224/29387 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83191 , H01L2224/83192 , H01L2224/83851 , H01L2224/92125 , H01L2224/92143 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06568 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。
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公开(公告)号：US09245827B2
公开(公告)日：2016-01-26
申请号：US14262693
申请日：2014-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
CPC classification number: H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
Abstract translation: 三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。 从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。 只有主芯片可以为通道提供负载。 可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。
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公开(公告)号：US20140233292A1
公开(公告)日：2014-08-21
申请号：US14262693
申请日：2014-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
CPC classification number: H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
Abstract translation: 三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。 从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。 只有主芯片可以为通道提供负载。 可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。
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