公开(公告)号：US10224272B2

公开(公告)日：2019-03-05

申请号：US16004539

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hwang Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Won-Il Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

公开(公告)号：US09997446B2

公开(公告)日：2018-06-12

申请号：US15468294

申请日：2017-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hwang Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Won-Il Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

公开(公告)号：US09230876B2

公开(公告)日：2016-01-05

申请号：US14267259

申请日：2014-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Woo Lee ,  Jong-Bo Shim ,  Kyoung-sei Choi

IPC: H01L23/48 ,  H01L23/36 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/36 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03312 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

Abstract translation: 堆叠型半导体封装包括：下半导体封装，包括下封装衬底，以及下半导体芯片，其安装在下封装衬底上，并且包括面向下封装衬底的顶表面的第一表面和与下封装衬底相对的第二表面 第一面; 上半导体封装，包括上封装基板和安装在上封装基板上的上半导体芯片; 连接下封装基板和上封装基板的封装间连接单元; 形成在下半导体芯片的第二表面上的散热构件; 以及互连单元，其形成在所述上封装基板的底表面上，并且粘附到所述散热构件以连接所述下半导体芯片和所述上封装基板。

公开(公告)号：US08829686B2

公开(公告)日：2014-09-09

申请号：US13678205

申请日：2012-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sun Hong ,  Young-Min Kim ,  Jung-Woo Kim ,  Min-Ok Na ,  Hyo-Chang Ryu ,  Jong-Bo Shim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/29 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

Abstract translation: 包装包装组件包括第一和第二包装以及定位在第一和第二包装之间并将第一和第二包装彼此粘合的粘合部件。 第一封装可以包括具有第一表面和第二表面的第一衬底，第一表面和第二表面彼此面对并且包括形成在第一表面上的焊盘焊盘，形成在第一表面上的第一半导体芯片和封装第一表面的第一密封剂构件， 所述第一半导体芯片并且包括与所述第一半导体芯片间隔开的通孔，并且暴露所述焊盘焊盘和形成在所述第一半导体芯片和所述通孔之间的沟槽，并且其中所述沟槽的至少一部分填充有粘附 会员资料

公开(公告)号：US20130187288A1

公开(公告)日：2013-07-25

申请号：US13678205

申请日：2012-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sun Hong ,  Young-Min Kim ,  Jung-Woo Kim ,  Min-Ok Na ,  Hyo-Chang Ryu ,  Jong-Bo Shim

IPC: H01L23/498

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

Abstract translation: 包装包装组件包括第一和第二包装以及定位在第一和第二包装之间并将第一和第二包装彼此粘合的粘合部件。 第一封装可以包括具有第一表面和第二表面的第一衬底，第一表面和第二表面彼此面对并且包括形成在第一表面上的焊盘焊盘，形成在第一表面上的第一半导体芯片和封装第一表面的第一密封剂构件， 所述第一半导体芯片并且包括与所述第一半导体芯片间隔开的通孔，并且暴露所述焊盘焊盘和形成在所述第一半导体芯片和所述通孔之间的沟槽，并且其中所述沟槽的至少一部分填充有粘附 会员资料

公开(公告)号：US10750112B2

公开(公告)日：2020-08-18

申请号：US16129010

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang Kim ,  Hyo-Eun Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Sang-Uk Han

IPC: H04N5/369 ,  H04N5/225 ,  G02B5/20 ,  H01L27/146

Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

公开(公告)号：US10199319B2

公开(公告)日：2019-02-05

申请号：US15485794

申请日：2017-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Bo Shim ,  Sang-Uk Han ,  Yun-Seok Choi ,  Ji-Hwang Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

公开(公告)号：US08922008B2

公开(公告)日：2014-12-30

申请号：US13834475

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Yun Myung ,  Yong-Hwan Kwon ,  Jong-Bo Shim ,  Moon-Gi Cho

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Abstract translation: 凸块结构包括第一凸块和第二凸块。 第一凸块设置在基板的连接焊盘上。 第一凸起包括具有第一宽度的下部，具有小于第一宽度的第二宽度的中间部分，以及具有大于第二宽度的第三宽度的上部。 第二凸块设置在第一凸块的上部。