公开(公告)号：US07154186B2

公开(公告)日：2006-12-26

申请号：US10803464

申请日：2004-03-18

Applicant: Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/48

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

公开(公告)号：US07081666B2

公开(公告)日：2006-07-25

申请号：US11051061

申请日：2005-02-04

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495 ,  H01L23/28

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

公开(公告)号：US06953998B2

公开(公告)日：2005-10-11

申请号：US10754095

申请日：2003-12-29

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/14 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L23/145 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the die serves as a drain connection while the solder balls serve as the source and gate connections.

Abstract translation: 不包括成型体或封装的半导体器件。 半导体器件包括衬底和耦合到衬底的管芯。 芯片耦合到衬底，使得假设MOSFET型器件的管芯的源极和栅极区域耦合到衬底。 焊球邻近管芯设置，使得当半导体器件耦合到印刷电路板时，裸片的暴露表面用作漏极连接，而焊球用作源极和栅极连接。

公开(公告)号：US06949410B2

公开(公告)日：2005-09-27

申请号：US10607633

申请日：2003-06-27

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23/48 ,  H01L21/76 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US20050133893A1

公开(公告)日：2005-06-23

申请号：US11051061

申请日：2005-02-04

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/60 ,  H01L23/495 ,  H01L21/48 ,  H01L23/10

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

公开(公告)号：US06891256B2

公开(公告)日：2005-05-10

申请号：US10271654

申请日：2002-10-15

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/50 ,  H01L23/28 ,  H01L23/10 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract translation: 本发明的实施例涉及半导体管芯封装。 本发明的一个实施例涉及一种半导体管芯封装，其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构被耦合 （c）栅极引线结构，其耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料，其中所述模制材料暴露所述半导体管芯的所述第二表面，以及 源极引线结构的主表面。

公开(公告)号：US20050012225A1

公开(公告)日：2005-01-20

申请号：US10852732

申请日：2004-05-24

Applicant: Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

Inventor： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

IPC: H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/48 ,  H01L23/52

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.

Abstract translation: 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US06720642B1

公开(公告)日：2004-04-13

申请号：US09464885

申请日：1999-12-16

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23495

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US06683375B2

公开(公告)日：2004-01-27

申请号：US09881787

申请日：2001-06-15

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L2348

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2924/013

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract translation: 公开了一种处理半导体衬底的方法。 该方法包括在具有导电区域的半导体衬底上提供具有孔的掩模。 掩模中的孔设置在导电区上。 将预先形成的导电柱放置在孔中并结合到导电区。