公开(公告)号：US06329045B1

公开(公告)日：2001-12-11

申请号：US09505988

申请日：2000-02-17

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Hiroyuki Handa

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Hiroyuki Handa

IPC分类号： B32B3100

CPC分类号： B29C43/18 ,  B29K2101/10 ,  B29L2031/3061 ,  C04B26/10 ,  C04B2111/00844 ,  C04B2111/92 ,  C08K3/01 ,  C09K5/14 ,  H01L2924/0002 ,  H05K1/0373 ,  H05K3/022 ,  H05K3/202 ,  H05K2201/0209 ,  H05K2201/09118 ,  Y10S428/901 ,  Y10T428/24802 ,  Y10T428/24909 ,  Y10T428/24917 ,  Y10T428/252 ,  Y10T428/31529 ,  C04B14/303 ,  C04B20/008 ,  C04B20/1037 ,  C04B40/0071 ,  C04B40/0082 ,  C04B40/0616 ,  C04B41/4572 ,  C04B41/51 ,  C04B14/304 ,  C04B14/325 ,  H01L2924/00

摘要： A composition for substrate materials according to the present invention includes 70-95 wt. % of inorganic powder and 5-30 wt. % of thermosetting resin composition and is in a finely crushed condition. The composition for substrate materials is prepared, for example, by crushing into fine pieces and mixing the inorganic powder and the thermosetting resin composition. A heat conductive substrate is provided with an insulator body formed by heating and pressurizing said composition for substrate materials and a wiring pattern is provided in such a condition that it is exposed on the surface of the insulator body. A process for manufacturing the heat conductive substrate comprises forming said composition for substrate materials into the insulator body by casting the above mentioned composition for substrate materials into a metal mold to be heated and pressurized so that said thermosetting resin is cured.

摘要翻译： 根据本发明的用于基材的组合物包含70-95wt。 ％的无机粉末和5-30wt。 ％的热固性树脂组合物，并且处于细碎的状态。 用于基材的组合物例如通过粉碎成细片并混合无机粉末和热固性树脂组合物来制备。 导热基板设置有通过对基板材料的所述组合物进行加热和加压而形成的绝缘体，并且以暴露于绝缘体的表面的状态设置布线图案。 制造导热基材的方法包括通过将上述用于基材的组合物浇铸到待加热和加压的金属模具中以使所述热固性树脂固化，从而将用于基材的所述组合物形成绝缘体。

公开(公告)号：US06300686B1

公开(公告)日：2001-10-09

申请号：US09158299

申请日：1998-09-22

申请人： Koichi Hirano ,  Seiichi Nakatani

发明人： Koichi Hirano ,  Seiichi Nakatani

IPC分类号： H01L2348

CPC分类号： H01L24/81 ,  H01L21/486 ,  H01L23/13 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/00

摘要： A thermal conductive sheet including at least 70-95 weight parts of inorganic filler and 5-30 weight parts of thermosetting resin composition and having flexibility in an uncured state is prepared. Through-holes are formed in the thermal conductive sheet and a conductive resin composition is filled in the through-holes. The thermal conductive sheet and a semiconductor chip are overlapped to match positions of the through-holes formed in the thermal conductive sheet with those of the electrodes formed on the semiconductor chip. The thermal conductive sheet and the semiconductor chip are compressed while being heated and the thermal conductive sheet is cured and integrated with the semiconductor chip. An external lead electrode is formed on the thermal conductive sheet at a side opposite to the surface where the semiconductor chip is overlapped, and that is connected with the conductive resin composition. According to the above-mentioned configuration, a semiconductor package that is not required to be sealed by resin, and is excellent in reliability, air-tightness and thermal conductivity can be realized.

摘要翻译： 制备包含至少70-95重量份无机填料和5-30重量份热固性树脂组合物并且具有未固化状态的柔性的导热片。 在导热片中形成通孔，在通孔中填充导电性树脂组合物。 重叠导热片和半导体芯片，以匹配形成在导热片中的通孔的位置与形成在半导体芯片上的电极的位置。 导热片和半导体芯片被加热时被压缩，并且导热片被固化并与半导体芯片集成。 在导热片上与半导体芯片重叠的表面相对的一侧形成外部引线电极，并与导电树脂组合物连接。 根据上述结构，可以实现不需要被树脂密封并且可靠性，气密性和导热性优异的半导体封装。

公开(公告)号：US08975626B2

公开(公告)日：2015-03-10

申请号：US12863202

申请日：2009-11-13

申请人： Takeshi Suzuki ,  Kenichi Hotehama ,  Koichi Hirano ,  Seiichi Nakatani

发明人： Takeshi Suzuki ,  Kenichi Hotehama ,  Koichi Hirano ,  Seiichi Nakatani

IPC分类号： H01L33/08 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L29/66765 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/7869

摘要： There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprises a metal layer comprising a gate electrode, a source electrode and a drain electrode; a metal oxide film made from a metal which constitutes the metal layer and formed over a surface region of the metal layer; and a semiconductor layer formed above the gate electrode via the metal oxide film. In the flexible semiconductor device, uncovered portions, each of which is not covered with the metal oxide film, are locally formed in the surface region of the metal layer; and also electrical connections are formed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer via the uncovered portions.

摘要翻译： 提供了一种柔性半导体器件。 本发明的柔性半导体器件包括由栅电极，源电极和漏电极组成的金属层; 由金属制成的金属氧化物膜，其构成金属层并形成在金属层的表面区域上; 以及通过金属氧化物膜形成在栅极电极上方的半导体层。 在柔性半导体器件中，在金属层的表面区域局部形成未被金属氧化物膜覆盖的未覆盖部分， 并且还通过未覆盖部分在源电极和半导体层之间以及在漏电极和半导体层之间形成电连接。

公开(公告)号：US08691683B2

公开(公告)日：2014-04-08

申请号：US13046151

申请日：2011-03-11

申请人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

发明人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

IPC分类号： H01L21/56

CPC分类号： H01L21/563 ,  B23K35/0244 ,  H01L21/67144 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/1361 ,  Y02P70/613 ,  Y10T29/53178 ,  H01L2224/05599

摘要： [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.

摘要翻译： 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。 此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化， 芯片安装体。

公开(公告)号：US08593720B2

公开(公告)日：2013-11-26

申请号：US13383010

申请日：2011-04-14

申请人： Koichi Hirano ,  Masami Nakagawa ,  Seiichi Nakatani

发明人： Koichi Hirano ,  Masami Nakagawa ,  Seiichi Nakatani

IPC分类号： G02B26/00 ,  G09G3/34

CPC分类号： G09F9/372 ,  G02F1/167 ,  G02F2001/1676 ,  G02F2201/18 ,  G09F9/301 ,  G09F15/0075

摘要： Provided is an electronic paper that permits a high-quality, large area to be easily created. Also provided is a method for producing the electronic paper. The electronic paper comprises: a first substrate upon which first electrodes are formed and a second substrate upon which second electrodes are formed, said first substrate and second substrate disposed so as to face each other; and a plurality of cell spaces constituting pixels between said first substrate and second substrate. The first substrate comprises a plurality of first sheet members, each having a first electrode formed thereon. By disposing a cover substrate on said first sheet members, each with a partition wall therebetween, a plurality of subsheet formations comprising the plurality of cell spaces partitioned by the partition walls are formed, and the first electrodes are connected in between adjacent subsheet formations.

摘要翻译： 提供了允许容易地创建高质量，大面积的电子纸。 还提供了一种用于生产电子纸的方法。 电子纸包括：形成有第一电极的第一基板和形成有第二电极的第二基板，所述第一基板和第二基板彼此相对配置; 以及在所述第一基板和第二基板之间构成像素的多个单元空间。 第一衬底包括多个第一片构件，每个第一片构件具有形成在其上的第一电极。 通过将覆盖基板设置在所述第一板状部件上，每个在其间具有隔壁，形成包括由隔壁分隔的多个电池单元的多个子片形成层，并且第一电极连接在相邻的子片层之间。

公开(公告)号：US20130168681A1

公开(公告)日：2013-07-04

申请号：US13821352

申请日：2012-02-21

申请人： Takeshi Suzuki ,  Koichi Hirano ,  Shinobu Masuda

发明人： Takeshi Suzuki ,  Koichi Hirano ,  Shinobu Masuda

IPC分类号： H01L29/66 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L21/0274 ,  H01L23/544 ,  H01L27/3262 ,  H01L29/78603 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2227/323 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method for manufacturing a flexible semiconductor device. The method of the flexible semiconductor device according to the present invention comprises the steps of: (i) forming an insulating layer on one of principal surfaces of a metal foil; (ii) forming a semiconductor layer on the insulating layer, and then forming source and drain electrodes so that the source and drain electrodes contact with the semiconductor layer; (iii) forming a flexible film layer so that the flexible film layer covers the semiconductor layer and the source and drain electrodes; (iv) forming vias in the flexible film layer, and thereby a semiconductor device precursor is provided; and (v) subjecting the metal foil to a processing treatment, and thereby forming a gate electrode from the metal foil, wherein, in the step (v) of the processing treatment of the metal foil, the gate electrode is formed in a predetermined position by using at least one of the vias of the semiconductor device precursor as an alignment marker.

摘要翻译： 提供了一种用于制造柔性半导体器件的方法。 根据本发明的柔性半导体器件的方法包括以下步骤：（i）在金属箔的主表面之一上形成绝缘层; （ii）在所述绝缘层上形成半导体层，然后形成源电极和漏电极，使得所述源极和漏极与所述半导体层接触; （iii）形成柔性膜层，使得柔性膜层覆盖半导体层和源极和漏极; （iv）在柔性膜层中形成通孔，从而提供半导体器件前体; 和（v）对所述金属箔进行处理处理，从而从所述金属箔形成栅电极，其中在所述金属箔的所述加工处理的步骤（v）中，所述栅电极形成在预定位置 通过使用半导体器件前体的至少一个通孔作为对准标记。

公开(公告)号：US08367488B2

公开(公告)日：2013-02-05

申请号：US13054049

申请日：2010-02-05

申请人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano

发明人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78603 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78681 ,  H01L29/7869 ,  H01L2224/24195 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2924/3511 ,  H01L2924/3512

摘要： A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.

摘要翻译： 一种方法包括制备通过顺序堆叠第一金属层10，无机绝缘层20，半导体层30和第二金属层40而形成的多层膜80的步骤; 通过蚀刻第二金属层40形成由第二金属层40构成的源电极42s和漏电极42d; 将树脂层50压接到设置有源电极42s和漏电极42d的多层膜80的表面，以将树脂层50中的源电极42s和漏电极42d嵌入; 以及通过蚀刻第一金属层10形成由第一金属层10构成的栅极电极10g。无机绝缘层20g用作栅极绝缘膜。 半导体层30用作沟道。

公开(公告)号：US08063486B2

公开(公告)日：2011-11-22

申请号：US11748111

申请日：2007-05-14

申请人： Koichi Hirano ,  Tsukasa Shiraishi ,  Seiichi Nakatani ,  Tatsuo Ogawa

发明人： Koichi Hirano ,  Tsukasa Shiraishi ,  Seiichi Nakatani ,  Tatsuo Ogawa

IPC分类号： H01L23/48

CPC分类号： H05K1/0271 ,  H01L23/49811 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/09 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09109 ,  H01L2924/00 ,  H01L2224/05599

摘要： A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.

摘要翻译： 具有基材10和形成在基材10的至少一个主表面上的电极11的电路板1包括形成在电极11的内部和侧部中的至少一个中的易剥离部分12， 电极11和容易剥离部12之间的粘合强度小于电极11与基材10之间的粘合强度。可以提供具有高连接可靠性并能实现窄间距安装的电路板。

公开(公告)号：US20110133137A1

公开(公告)日：2011-06-09

申请号：US13027498

申请日：2011-02-15

申请人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita

发明人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita

IPC分类号： H01B1/22

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1141 ,  H01L2224/1152 ,  H01L2224/11524 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/293 ,  H01L2224/294 ,  H01L2224/73104 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0425 ,  H05K2203/087 ,  H05K2203/1178 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.

摘要翻译： 一种倒装芯片安装工艺，其中半导体芯片和电路基板电连接。 该方法包括制备其上形成有第一多个电极的半导体芯片和形成有第二多个电极的电路基板的步骤; 在电路基板的表面上提供组合物，该表面设置有第二多个电极; 使所述半导体芯片与所述组合物的表面接触，使得所述第一多个电极与所述第二多个电极相对; 并且加热电路基板，从而在第一多个电极和第二多个电极之间形成包括构成分散在组合物中的金属颗粒的金属组分的电连接。 此外，在半导体芯片和电路基板之间形成热固性树脂层。

公开(公告)号：US20100283054A1

公开(公告)日：2010-11-11

申请号：US12681445

申请日：2009-07-30

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Tatsuo Ogawa ,  Takashi Ichiryu ,  Takeshi Suzuki

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Tatsuo Ogawa ,  Takashi Ichiryu ,  Takeshi Suzuki

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78651 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1266 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869

摘要： There is provided a method for manufacturing a flexible semiconductor device characterized by comprising (i) a step of forming an insulating film on the upper surface of metal foil, (ii) a step of forming an extraction electrode pattern on the upper surface of the metal foil, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the extraction electrode pattern, (iv) a step of forming a sealing resin layer on the upper surface of the metal foil in such a manner that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) a step of forming electrodes by etching the metal foil, wherein the metal foil is used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). A TFT element can be fabricated by a simple process because the metal foil serving as the support need not be finally stripped off. Further, a high-temperature process can be introduced to the fabrication of the insulating film and the semiconductor layer because the metal foil is used as the support, whereby the TFT characteristic is improved.

摘要翻译： 提供了一种制造柔性半导体器件的方法，其特征在于包括：（i）在金属箔的上表面上形成绝缘膜的步骤，（ii）在金属的上表面上形成引出电极图案的步骤 箔，（iii）以半导体层与引出电极图案接触的方式在绝缘膜上形成半导体层的步骤，（iv）在所述绝缘膜的上表面上形成密封树脂层的步骤 金属箔以密封树脂层覆盖半导体层和引出电极图案，以及（v）通过蚀刻金属箔形成电极的步骤，其中金属箔用作绝缘膜的支撑体， （i）〜（iv）中形成的并用作（v）中的电极的构成材料的引出电极图案，半导体层和密封树脂层。 由于作为支撑体的金属箔不需要最终被剥离，所以可以通过简单的工艺制造TFT元件。 此外，由于使用金属箔作为支撑体，因此可以将绝缘膜和半导体层的制造引入高温处理，从而提高TFT特性。