公开(公告)号：US20080237706A1

公开(公告)日：2008-10-02

申请号：US12002437

申请日：2007-12-17

Applicant: Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

Inventor： Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

IPC: H01L29/78

CPC classification number: H01L29/735 ,  H01L21/761 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/092 ,  H01L29/7322 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region.

Abstract translation: 形成在第一导电类型的衬底中的横向MOSFET包括形成在衬底的表面上的栅极电介质层顶部的栅极，第二导电类型的漏极区域，第二导电类型的源极区域和主体区域 的第一导电类型在栅极下延伸。 体区域可以具有非单调垂直掺杂分布，其中位于衬底中的部分位于比衬底中较浅的部分具有更高的掺杂浓度的部分。 横向MOSFET可以以漏极为中心，源极区域和围绕漏极区域的可选的介电填充沟槽。

公开(公告)号：US20080237704A1

公开(公告)日：2008-10-02

申请号：US12002358

申请日：2007-12-17

Applicant: Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

Inventor： Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

IPC: H01L27/06

CPC classification number: H01L21/823878 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/732 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.

Abstract translation: 用于半导体器件的隔离结构包括地板隔离区域，位于地板隔离区域上方的电介质填充沟槽以及从沟槽底部向下延伸到地板隔离区域的侧壁隔离区域。 该结构在半导体衬底中提供了较深的隔离袋，同时限制了必须在衬底中被蚀刻的沟槽的深度。 在隔离的袋中形成MOSFET。

公开(公告)号：US20080217662A1

公开(公告)日：2008-09-11

申请号：US12075814

申请日：2008-03-14

Applicant: James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

Inventor： James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

IPC: H01L29/80 ,  H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

Abstract translation: 通过产生用于从设备的接地触点接收下焊线的至少一个补充的下焊垫部分来增强横向导电的半导体器件封装中的空间的有效利用。 补充的底部部分可以占据以前由非整体引线占据的包装的端部或侧面的区域。 通过接收衬底下焊接线，补充的双面部分允许主凹版的更大面积被具有较大面积的模具占据，从而提高了封装的空间效率。

公开(公告)号：US20080197446A1

公开(公告)日：2008-08-21

申请号：US12072653

申请日：2008-02-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/762

CPC classification number: H01L21/765 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/861

Abstract: Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract translation: 各种集成电路装置，特别是二极管，形成在隔离结构内部，该隔离结构包括底板隔离区域和从衬底的表面延伸到地板隔离区域的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。 描述了通过使用保护环将基底隔离区域延伸超过沟槽并形成漂移区域来终止隔离结构的各种技术。

公开(公告)号：US20080191679A1

公开(公告)日：2008-08-14

申请号：US12032673

申请日：2008-02-16

Applicant: Richard K. Williams

Inventor： Richard K. Williams

IPC: G05F1/00

CPC classification number: H02M3/155 ,  H01L29/8128

Abstract: A Buck converter that includes a cascode switch comprising a series connected MESFET and MOSFET power switch. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter.

Abstract translation: 一个降压转换器，包括一个共源共栅开关，包括串联连接的MESFET和MOSFET电源开关。 共源共栅电源开关通常连接在电源和节点Vx之间。 节点Vx通过电感器连接到输出节点，并通过肖特基二极管或第二MESFET或两者接地。 控制电路驱动MESFET（和第二MESFET），使得电感器交替地连接到电池和接地。 在睡眠或待机模式期间，MOSFET关闭，以最大限度地减少通过MESFET的漏电流。 因此，与MESFET相比，MOSFET以低频率切换，并且对转换器中的开关损耗没有显着影响。

公开(公告)号：US20080186004A1

公开(公告)日：2008-08-07

申请号：US11307200

申请日：2006-01-26

Applicant: Richard K. Williams

Inventor： Richard K. Williams

IPC: G05F1/44 ,  H03K17/687

CPC classification number: H02M3/156 ,  H01L29/8128 ,  H03K17/08142 ,  H03K2217/0036

Abstract: A MESFET based boost converter includes an N-channel MESFET connected to a node Vx. An inductor connects the node Vx to a battery or other power source. The node Vx is also connected to an output node via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to ground and to the output node. The maximum voltage impressed across the low side MESFET is optionally clamped by a Zener diode. In some implementations, the MESFET is connected in series with a MOSFET. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter. In other implementations, more than one MESFET is connected in series with a MOSFET, the MOSFETs being switched off during periods of inactivity to suppress leakage currents.

Abstract translation: 基于MESFET的升压转换器包括连接到节点Vx的N沟道MESFET。 电感器将节点Vx连接到电池或其他电源。 节点Vx也通过肖特基二极管或第二MESFET或两者连接到输出节点。 控制电路驱动MESFET（和第二MESFET），使得电感器交替地连接到地和输出节点。 跨越低侧MESFET施加的最大电压可选择由齐纳二极管钳位。 在一些实现中，MESFET与MOSFET串联连接。 在睡眠或待机模式期间，MOSFET关闭，以最大限度地减少通过MESFET的漏电流。 因此，与MESFET相比，MOSFET以低频率切换，并且对转换器中的开关损耗没有显着影响。 在其他实现中，多个MESFET与MOSFET串联连接，MOSFET在不活动期间关闭，以抑制漏电流。

公开(公告)号：US20080135991A1

公开(公告)日：2008-06-12

申请号：US11609706

申请日：2006-12-12

Applicant: James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Teng Hui ,  Hongbo Yang ,  Zhou Ming ,  Anthony C. Tsui

Inventor： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Teng Hui ,  Hongbo Yang ,  Zhou Ming ,  Anthony C. Tsui

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49572 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/37124 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with a supported die through electrically conducting bumps or balls. By eliminating the need for a separate diepad and lateral isolation between an edge of the diepad and adjacent non-integral leads or pins, embodiments of packages fabricated by bump on leadframe (BOL) processes in accordance with embodiments of the present invention increase the space available to the die for a given package footprint. Embodiments of the present invention may also permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.

Abstract translation: 本发明的实施例涉及具有封装的引线框的半导体器件封装，其通过导电凸块或球与支撑的裸片电连通。 通过消除对单板的边缘和相邻的非整体引线或引脚之间的单独的双面和侧向隔离的需要，根据本发明的实施例的通过引线框架上的凸起（BOL）工艺制造的封装的实施例增加了可用的空间 给模具一个给定的封装足迹。 本发明的实施例还可以允许多个管芯和/或多个无源器件占据以前由diepad消耗的封装中的空间。 结果是灵活的封装过程，允许在传统的小型JEDEC规定的占地面积中，完整子系统所需的管芯和技术的组合。

公开(公告)号：US20080122006A1

公开(公告)日：2008-05-29

申请号：US11978901

申请日：2007-10-30

Applicant: Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chen

Inventor： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chen

IPC: H01L27/092

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

公开(公告)号：US07329551B2

公开(公告)日：2008-02-12

申请号：US11124439

申请日：2005-05-05

Applicant: Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

Inventor： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

IPC: H01L21/66

CPC classification number: H01L23/60 ,  H01L22/32 ,  H01L23/49562 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0266 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05138 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  Y10S257/904 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract translation: 半导体管芯具有用于诸如功率MOSFET的MOSFET的接合焊盘和用于ESD保护电路的单独的接合焊盘。 将焊盘连接在一起可使ESD保护电路起到保护MOSFET的作用。 在将焊盘连接在一起之前，ESD保护电路和/或MOSFET可以单独测试。 当测试MOSFET时，可以使用高于功能ESD保护电路的电压。 在倒装芯片封装中的引线接合或将管芯附接到衬底的封装工艺可以在测试之后连接焊盘。

公开(公告)号：US20070278568A1

公开(公告)日：2007-12-06

申请号：US11443745

申请日：2006-05-31

Applicant: Richard K. Williams ,  Donald Ray Disney ,  Jun-Wei Chen ,  Wai Tien Chan ,  HyungSik Ryu

Inventor： Richard K. Williams ,  Donald Ray Disney ,  Jun-Wei Chen ,  Wai Tien Chan ,  HyungSik Ryu

IPC: H01L29/76 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/761 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L27/098 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66106 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/66901 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

Abstract translation: 所有低温工艺都用于制造不包括外延层的衬底中的各种半导体器件。 这些器件包括非隔离的横向DMOS，非隔离的扩展漏极或漂移的MOS器件，横沟DMOS，隔离的横向DMOS，JFET和耗尽型器件以及P-N二极管钳位和整流器和结终端。 由于该工艺消除了对高温处理的需要并采用“植入式”掺杂剂分布，所以它们构成了模块化结构，其允许将器件添加或省略到IC中，而无需改变用于产生剩余器件的工艺。