公开(公告)号：US07977741B2

公开(公告)日：2011-07-12

申请号：US12939729

申请日：2010-11-04

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US07851281B2

公开(公告)日：2010-12-14

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L21/336

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20100182144A1

公开(公告)日：2010-07-22

申请号：US12376661

申请日：2007-08-06

申请人： Yoshihisa Yamashita ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Fumio Fukushima ,  Kuniaki Kiyosue

发明人： Yoshihisa Yamashita ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Fumio Fukushima ,  Kuniaki Kiyosue

IPC分类号： G08B1/08 ,  G06K19/077 ,  G06K19/06 ,  B32B38/10

CPC分类号： H01Q19/10 ,  G06K19/07749 ,  G06K19/07771 ,  H01Q1/2208 ,  H01Q17/00

摘要： Provided is a RFID magnetic sheet to be attached to an IC tag. The RFID magnetic sheet is provided with a plurality of stripe arranged layers (11a, 11b) whereupon a plurality of magnetic stripes (12) composed of a metal magnetic material are arranged at intervals, and a resin film (10) interposed between the respective stripe arranged layers. The arrangement relationship between the stripe arranged layers is set so that the magnetic stripes on each of the stripe arranged layers intersect with the magnetic stripes on the other stripe arranged layer in a planar shape.

摘要翻译： 提供了要附接到IC标签的RFID磁性片。 RFID磁性片设置有多个条状布置层（11a，11b），由此间隔地布置由金属磁性材料构成的多个磁条（12），并且在相应条带之间插入树脂膜（10） 布置层。 设置条纹布置层之间的布置关系，使得每个条纹布置层上的磁条与另一个条纹布置层上的磁条以平面形状相交。

公开(公告)号：US20100181558A1

公开(公告)日：2010-07-22

申请号：US12667297

申请日：2008-07-01

申请人： Yoshihisa Yamashita ,  Seiichi Nakatani

发明人： Yoshihisa Yamashita ,  Seiichi Nakatani

IPC分类号： H01L51/10 ,  H01L51/40

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L27/3274 ,  H01L51/0004

摘要： A semiconductor device having semiconductor elements disposed with higher density and a method for manufacturing the same are provided.An image display device employing the semiconductor device is also provided.A semiconductor device comprises a resin film having a through hole; and a semiconductor element comprising a gate electrode disposed on the inner wall of the through hole, an insulating layer that covers the gate electrode within the through hole, an organic semiconductor disposed on the insulating layer within the through hole, and a source electrode and a drain electrode which are electrically connected to the organic semiconductor.

摘要翻译： 提供了具有以更高密度设置的半导体元件的半导体器件及其制造方法。 还提供了采用半导体器件的图像显示装置。 半导体器件包括具有通孔的树脂膜; 以及半导体元件，包括设置在通孔的内壁上的栅电极，覆盖通孔内的栅电极的绝缘层，设置在通孔内的绝缘层上的有机半导体，以及源电极和 电极与有机半导体电连接。

公开(公告)号：US20100012936A1

公开(公告)日：2010-01-21

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8234 ,  B32B3/02

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20090008800A1

公开(公告)日：2009-01-08

申请号：US11909856

申请日：2006-03-14

申请人： Seiichi Nakatani ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Seiji Karashima

发明人： Seiichi Nakatani ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Seiji Karashima

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/83007 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/0695 ,  H01L2224/05599

摘要： The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217). Thereby, the flip chip mounted body with excellent productivity and reliability that can mount the semiconductor chip on the circuit board, and a method and an apparatus for mounting the flip chip mounted body are provided.

摘要翻译： 本发明的倒装芯片安装体包括：具有多个连接端子（211​​）的电路板（213）; 具有与所述连接端子相对设置的多个电极端子（207）的半导体芯片（206）。 在所述半导体芯片（206）的外周折叠具有设置在所述半导体芯片（206）的所述电极端子（207）的形成面的相反侧的盒状的多孔片（205） 在电极端子（207）的形成面侧与电路基板（213）接触，电路基板（213）的连接端子（211​​）和半导体芯片的电极端子（207） 206）通过焊料层（215）电连接，并且电路板（213）和半导体芯片（206）由树脂（217）固定。 因此，提供了将半导体芯片安装在电路板上的优异的生产率和可靠性的倒装芯片安装体以及安装倒装芯片安装体的方法和装置。

公开(公告)号：US20080197173A1

公开(公告)日：2008-08-21

申请号：US11579505

申请日：2006-04-25

申请人： Takashi Kitae ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Yoshihisa Yamashita

发明人： Takashi Kitae ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Yoshihisa Yamashita

IPC分类号： B23K31/02 ,  B23K1/20

CPC分类号： H05K3/3484 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/1152 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/323 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/10977 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/043 ,  H05K2203/0465 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099

摘要： [Problem] To provide a method for forming solder bumps for realizing high density mounting and a highly reliable method for mounting a semiconductor device.[Means for Solving Problem] A flat plate 10 or 30 having a plurality of projections 12 or recesses 32 thereon is prepared; the flat plate is aligned to oppose an electronic component 14 or 34 and a resin composition 18 or 19 including a solder powder 22 or 23 is supplied to a gap between the flat plate and the electronic component; the resin composition is annealed to melt the solder powder included in the resin composition for growing the solder powder up to the level of the surface of the flat plate by allowing the melted solder powder to self-assemble on terminals 16 or 36, so as to form solder bumps 24 or 38 on the terminals; and the flat plate is removed after cooling and solidifying the solder bumps. Thus, the solder bumps 24 or 38 having pits 24a corresponding to the projections 12 or having projections 38a corresponding to the recesses 32 are formed.

摘要翻译： [问题]提供一种形成用于实现高密度安装的焊料凸块的方法和用于安装半导体器件的高可靠性方法。 [解决问题的手段]准备在其上具有多个突起12或凹部32的平板10或30; 平板对准电子部件14或34，并且包括焊料粉末22或23的树脂组合物18或19被供应到平板和电子部件之间的间隙; 对树脂组合物进行退火，通过使熔融的焊料粉末在端子16或36上自组装，将包含在用于生长焊料粉末的树脂组合物中的焊料粉末熔化至平板表面的高度，从而 在端子上形成焊料凸块24或38; 并且在冷却并固化焊料凸块之后去除平板。 因此，形成具有对应于突起12的凹坑24a或具有对应于凹部32的突起38a的焊料凸块24或38。

公开(公告)号：US20080017995A1

公开(公告)日：2008-01-24

申请号：US11662286

申请日：2005-09-07

申请人： Seiji Karashima ,  Yoshihisa Yamashita ,  Satoru Tomekawa ,  Takashi Kitae ,  Seiichi Nakatani

发明人： Seiji Karashima ,  Yoshihisa Yamashita ,  Satoru Tomekawa ,  Takashi Kitae ,  Seiichi Nakatani

IPC分类号： H01L23/12 ,  H01L21/603

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1152 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/293 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/818 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83886 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/0425 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/254 ,  Y10T428/31681 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/05599

摘要： There is provided a flip chip mounting process which is high in productivity and reliability, and thus can be applicable to the flip chip mounting of the next-generation LSI. This flip chip mounting process comprises the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. This heating step is carried out at a temperature higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21). Finally, the resin is cured so as to secure the semiconductor chip (20) to the wiring substrate (10).

摘要翻译： 提供了一种倒装芯片安装工艺，其生产率和可靠性高，因此可以适用于下一代LSI的倒装芯片安装。 这种倒装芯片安装工艺包括以下步骤：将含有焊料粉末的树脂（13）和对流添加剂（12）提供到具有多个电极端子（11）的布线基板（10）上，然后将半导体芯片（20） 具有与供给的树脂（13）的表面接触的多个连接端子（11），然后将布线基板（10）加热到使焊料粉末熔化的温度。 该加热步骤在高于对流添加剂（12）的沸点的温度下进行，以允许沸腾对流添加剂（12）在树脂（12）内移动。 在该加热步骤中，使熔融的焊料粉末自组装到布线基板（10）的每个电极端子（11）与半导体芯片的每个连接端子（21）之间的区域中，以形成每个 电极端子（11）和每个连接端子（21）。 最后，树脂被固化，以将半导体芯片（20）固定到布线基板（10）上。

公开(公告)号：US07321496B2

公开(公告)日：2008-01-22

申请号：US11079316

申请日：2005-03-15

申请人： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

发明人： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K3/386 ,  H01L51/424 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

摘要： A flexible substrate comprises: a film; an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.

摘要翻译： 柔性基板包括：膜; 形成在所述膜的前表面和所述膜的后表面中的每一个上的绝缘树脂层，所述后表面与所述前表面相对; 嵌入到形成在膜的前表面上的绝缘树脂层中的前侧布线图案和嵌入在形成在膜的背面上的绝缘树脂层中的背面布线图案; 以及位于前侧布线图案和背面布线图案之间的通孔，用于将前侧布线图案和背面布线图案电连接，其中形成在每个正面上的绝缘树脂层 薄膜的表面和背面比薄膜厚。

公开(公告)号：US07314276B2

公开(公告)日：2008-01-01

申请号：US11008918

申请日：2004-12-13

申请人： Shoji Koike ,  Yoshihisa Yamashita ,  Kohei Watanabe ,  Hayato Ida

发明人： Shoji Koike ,  Yoshihisa Yamashita ,  Kohei Watanabe ,  Hayato Ida

IPC分类号： G01D11/00

CPC分类号： B41J11/0015 ,  C09D11/38

摘要： The present invention provides an ink-jet recording method for forming an image by applying an ink to a recording medium, wherein the ink used contains at least water, a pigment, a dispersing agent for dispersing the pigment and an acid form of an anionic surfactant. The ink has a surface tension higher than the critical surface tension of the recording medium. The ink is applied to the recording medium, and the surface tension of the ink is reduced to a surface tension below the critical surface tension of the recording medium after contacting the recording medium.

摘要翻译： 本发明提供了一种用于通过向记录介质施加油墨来形成图像的喷墨记录方法，其中使用的油墨至少含有水，颜料，用于分散颜料的分散剂和酸形式的阴离子表面活性剂 。 油墨的表面张力高于记录介质的临界表面张力。 油墨被施加到记录介质上，并且在接触记录介质之后，油墨的表面张力降低到低于记录介质的临界表面张力的表面张力。