公开(公告)号：US20150069566A1

公开(公告)日：2015-03-12

申请号：US14166176

申请日：2014-01-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yuichi Tagami ,  Shigeyuki Sakura

IPC: H01L31/105

CPC classification number: H01L31/105 ,  H01L31/02005 ,  H01L31/02164 ,  H01L31/022408 ,  H01L31/03529 ,  Y02E10/50

Abstract: According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer.

Abstract translation: 根据一个实施例，光电二极管包括第一导电类型的第一半导体层，第二导电类型的第二半导体层，第一导电类型的第三半导体层和膜。 第二半导体层设置在第一半导体层中。 第三半导体层设置在第一半导体层中以围绕第二半导体层。 第二和第三半导体层的一端分别位于第一半导体层的上表面。 第一至第三半导体层分别包括第一至第三杂质浓度。 第二和第三杂质浓度高于第一杂质浓度。 该膜设置在第三半导体层之上，并且阻挡光进入第三半导体层的附近。

公开(公告)号：US08962371B2

公开(公告)日：2015-02-24

申请号：US14126490

申请日：2012-11-21

Applicant: Beijing BOE Optoelectronics Technology Co., Ltd.

Inventor： Shaoying Xu ,  Zhenyu Xie ,  Xu Chen

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/14692 ,  H01L27/14687 ,  H01L31/105

Abstract: A method for fabricating a sensor, comprises: forming, on a base substrate, a pattern of a data line (31), a pattern of a drain electrode (34), a pattern of a source electrode (33), a pattern of a receive electrode (39), a pattern of a photodiode (40) and a pattern of a transparent electrode (41); forming a pattern of an ohmic layer by using a first patterning process; forming a pattern of an active layer by using a second patterning process; forming a pattern of a gate insulating layer by using a third patterning process; and forming a pattern of a gate line (30), a pattern of a gate electrode (38) and a pattern of a bias electrode (42) by using a fourth patterning process. Such a method can reduce the number of mask as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the defect-free rate.

Abstract translation: 一种用于制造传感器的方法，包括：在基底基板上形成数据线（31）的图案，漏电极（34）的图案，源电极（33）的图案， 接收电极（39），光电二极管（40）的图案和透明电极（41）的图案。 通过使用第一图案化工艺形成欧姆层的图案; 通过使用第二图案化工艺形成有源层的图案; 通过使用第三图案化工艺形成栅极绝缘层的图案; 以及通过使用第四图案化工艺形成栅极线（30）的图案，栅极（38）的图案和偏置电极（42）的图案。 这种方法可以减少掩模的数量和生产成本，并且简化了生产过程，从而显着提高了生产能力和无缺陷率。

公开(公告)号：US20150035014A1

公开(公告)日：2015-02-05

申请号：US13959081

申请日：2013-08-05

Applicant: Raytheon Company

Inventor： John J. Drab ,  Justin Gordon Adams Wehner ,  Christian M. Boemler

IPC: H01L27/146 ,  H01L29/868

CPC classification number: H01L27/14643 ,  H01L27/1446 ,  H01L27/14605 ,  H01L27/14649 ,  H01L27/14689 ,  H01L29/868 ,  H01L31/105

Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

Abstract translation: 一种半导体结构，具有：硅结构; 以及形成在所述硅结构中的多个横向间隔开的PiN二极管; 并且所述硅结构的表面被配置为减少穿过所述PiN二极管的反向偏置漏电流。 在一个实施例中，栅极电极结构设置在硅结构的表面上，栅极电极结构具有设置在相邻的二极管对之间的部分，栅极结构被偏置以防止通过二极管的漏电流。

公开(公告)号：US08946842B2

公开(公告)日：2015-02-03

申请号：US14017708

申请日：2013-09-04

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Ryuji Masuyama ,  Yoshihiro Yoneda ,  Hideki Yagi ,  Naoko Inoue

IPC: H01L31/0232 ,  H01L21/00 ,  G02B6/00 ,  G02B6/42

CPC classification number: H01L31/02325 ,  G02B6/42 ,  H01L31/0232 ,  H01L31/105

Abstract: A method for manufacturing an optical waveguide receiver includes the steps of growing first and second stacked semiconductor layer sections, the second stacked semiconductor layer section including a core layer and a cladding layer; forming a first mask including first and second portions; etching the first and second stacked semiconductor layer sections by using the first mask, the first and second stacked semiconductor layer sections covered with the first portion being etched in a mesa structure, the second stacked semiconductor layer section covered with the second portion being etched in a terrace-shaped structure; removing the second portion from the first mask with the first portion left; selectively etching the cladding layer until exposing a surface of the core layer; and sequentially forming a first metal layer, an insulating film, and a second metal layer on the core layer exposed in the step of selectively etching the cladding layer.

Abstract translation: 一种光波导接收机的制造方法，其特征在于，包括生长第1和第2层叠半导体层部的工序，所述第2层叠半导体层部包含芯层和包覆层。 形成包括第一和第二部分的第一掩模; 通过使用第一掩模蚀刻第一和第二层叠半导体层部分，被第一部分覆盖的第一和第二层叠半导体层部分被蚀刻在台面结构中，被第二部分覆盖的第二堆叠半导体层部分被蚀刻在 露台形结构; 从所述第一掩模移除所述第二部分，所述第一部分留下; 选择性地蚀刻包层，直到暴露核心层的表面; 并且在选择性地蚀刻包覆层的步骤中露出的芯层上依次形成第一金属层，绝缘膜和第二金属层。

公开(公告)号：US08940573B2

公开(公告)日：2015-01-27

申请号：US13838241

申请日：2013-03-15

Applicant: Sumitomo Electric Device Innovations, Inc.

Inventor： Yuji Koyama

IPC: H01L21/00 ,  H01L33/60 ,  H01L31/0232 ,  H01L31/052 ,  H01L31/075 ,  H01L31/105 ,  H01L31/0224

CPC classification number: H01L33/60 ,  H01L31/022416 ,  H01L31/02327 ,  H01L31/052 ,  H01L31/053 ,  H01L31/0543 ,  H01L31/056 ,  H01L31/075 ,  H01L31/105 ,  Y02E10/52 ,  Y02E10/548

Abstract: A method of manufacturing a semiconductor light-receiving element includes: forming a semiconductor layer structure having a one-conductivity-type semiconductor layer having a first conduction type located on a side of light incidence, an opposite-conductivity-type semiconductor layer having a second conduction type opposite to the first conduction type, and a light-absorbing layer between the one-conductivity-type semiconductor layer and the opposite-conductivity type semiconductor layer, the opposite-conductivity-type semiconductor layer having a structure in which a first semiconductor layer comprised of a binary mixed crystal, a second semiconductor layer comprised of a three-or-more-element mixed crystal, and a third semiconductor layer comprised of a three-or-more-element mixed crystal having an energy gap smaller than that of the second semiconductor layer are laminated in this order from the light incidence side; forming a metal film that is in contact with the third semiconductor layer; and performing a thermal process after the forming of the metal film.

Abstract translation: 一种制造半导体光接收元件的方法包括：形成具有位于光入射侧的具有第一导电类型的一导电型半导体层的半导体层结构，具有第二导电类型的导电型半导体层 与第一导电型相反的导电型，以及在一导电型半导体层和相反导电型半导体层之间的光吸收层，具有如下结构的相反导电型半导体层，其中第一半导体层 由二元混晶构成的第二半导体层，由三元素或更多元素的混晶构成的第二半导体层，以及由具有小于等于或等于 第二半导体层从光入射侧依次层叠; 形成与所述第三半导体层接触的金属膜; 并且在形成金属膜之后进行热处理。

公开(公告)号：US08938134B2

公开(公告)日：2015-01-20

申请号：US13724926

申请日：2012-12-21

Applicant: Alcatel-Lucent, USA Inc.

Inventor： Long Chen

IPC: G02F1/035 ,  H01L21/00 ,  G02F1/025 ,  H01L33/58 ,  H01L31/103 ,  H01L31/105 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/12002 ,  G02B6/12004 ,  H01L31/1035 ,  H01L31/105 ,  H01L33/58

Abstract: An apparatus comprising an optical modulator, wherein the optical modulator comprises a planar substrate, a first III-V semiconductor layer on the substrate, and a silicon layer on the substrate. The optical modulator includes a planar semiconductor optical waveguide having a hybrid optical core, the hybrid optical core including vertically adjacent lateral portions of the first III-V semiconductor layer and the silicon layer.

Abstract translation: 一种包括光调制器的装置，其中所述光调制器包括平面基板，所述基板上的第一III-V半导体层和所述基板上的硅层。 光调制器包括具有混合光纤芯的平面半导体光波导，该混合光纤芯包括第一III-V半导体层和硅层的垂直相邻横向部分。

公开(公告)号：US08890272B2

公开(公告)日：2014-11-18

申请号：US13207372

申请日：2011-08-10

Applicant: Michael Tkachuk

Inventor： Michael Tkachuk

IPC: H01L31/102 ,  H01L31/105

CPC classification number: H01L31/105 ,  H01L31/03046 ,  H01L31/101 ,  Y02E10/544

Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.

Abstract translation: 提供了一种光电检测器，包括：辐射吸收半导体区域和由隔离半导体区域分隔开并且与隔离半导体区域接触的收集半导体区域; 其中，至少在不存在所施加的偏置电压的情况下，所述势垒能量与所述势垒半导体区域的导带能量之间的带隙偏离所述辐射的价带能量和导带能量之间的带隙 吸收半导体区域，以便在辐射吸收半导体区域和集电半导体区域之间形成阻挡少数载流子从辐射吸收半导体区域到收集半导体区域的能量势垒。 还提供了一种制造光电检测器的方法。

公开(公告)号：US08889455B2

公开(公告)日：2014-11-18

申请号：US12633297

申请日：2009-12-08

Applicant: Peter Duane ,  Young-June Yu ,  Munib Wober

Inventor： Peter Duane ,  Young-June Yu ,  Munib Wober

IPC: H01L21/28 ,  H01L21/02 ,  H01L31/105 ,  H01L31/103 ,  H01L31/0352 ,  H01L27/146

CPC classification number: H01L31/0352 ,  G01J1/42 ,  G01J5/20 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/02664 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14665 ,  H01L27/14669 ,  H01L27/14683 ,  H01L31/02327 ,  H01L31/035227 ,  H01L31/101 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18 ,  Y10S977/762

Abstract: An embodiment relates to a method of manufacturing a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.

Abstract translation: 一个实施方案涉及一种制造器件的方法，该器件包括具有正面和背面的衬底，设置在背面的纳米线和设置在前侧的图像感测电路，其中纳米线被配置为两者 用于传输高达选择波长的波长的信道和有源元件，以检测通过纳米线传输的选择波长的波长。

公开(公告)号：US20140319463A1

公开(公告)日：2014-10-30

申请号：US14260110

申请日：2014-04-23

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Kei FUJII ,  Kaoru SHIBATA ,  Katsushi AKITA

IPC: H01L31/0352 ,  H01L31/0304 ,  H01L31/0236 ,  H01L31/18

CPC classification number: H01L31/035236 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02587 ,  H01L21/0262 ,  H01L31/03046 ,  H01L31/105 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

Abstract: An epitaxial wafer of the present invention includes a substrate composed of a III-V compound semiconductor, a multiple quantum well structure composed of a III-V compound semiconductor and located on the substrate, and a top layer composed of a III-V compound semiconductor and located on the multiple quantum well structure. The substrate has a plane orientation of (100) and an off angle of −0.030° or more and +0.030° or less, and a surface of the top layer has a root-mean-square roughness of less than 10 nm.

Abstract translation: 本发明的外延片包括由III-V族化合物半导体构成的基板，由III-V族化合物半导体构成的位于基板上的多量子阱结构，以及由III-V族化合物半导体 并位于多量子阱结构上。 基板具有（100）的平面取向和-0.030°以上且+ 0.030°以下的偏离角，顶层的表面的均方根粗糙度小于10nm。

公开(公告)号：US08873893B2

公开(公告)日：2014-10-28

申请号：US13002884

申请日：2008-07-31

Applicant: Sagi Varghese Mathai ,  Shih-Yuan Wang

Inventor： Sagi Varghese Mathai ,  Shih-Yuan Wang

IPC: G02F1/01 ,  H01L31/0352 ,  H01L31/105 ,  G02B6/10 ,  B82Y20/00 ,  H01S5/34 ,  H01S5/50 ,  H01S5/10

CPC classification number: H01S5/341 ,  B82Y20/00 ,  G02B6/107 ,  H01L31/035227 ,  H01L31/035236 ,  H01L31/105 ,  H01S5/10 ,  H01S5/50 ,  H01S5/5018 ,  H01S5/5036

Abstract: A nano-wire optical block device for amplifying, modulating, and detecting an optical signal in a large-core hollow metallized waveguide. The nano-wire optical block device comprises a substrate with a plurality of nano-wires coupled to the substrate to form the nano-wire optical block. Each properly formed nano-wire is comprised of a p-doped region, an intrinsic region, and an n-doped region. The nano-wire optical block is operable to be inserted into the large-core hollow metallized waveguide to provide at least one of amplifying, modulating, and detecting the optical signal.

Abstract translation: 一种用于在大芯中空金属化波导中放大，调制和检测光信号的纳米线光学块装置。 纳米线光学块器件包括具有耦合到衬底的多个纳米线以形成纳米线光学块的衬底。 每个正确形成的纳米线由p掺杂区域，本征区域和n掺杂区域组成。 纳米线光学块可操作地插入到大芯中空金属化波导中以提供放大，调制和检测光信号中的至少一个。