公开(公告)号：US20170187343A1

公开(公告)日：2017-06-29

申请号：US15460750

申请日：2017-03-16

Applicant: INPHI CORPORATION

Inventor： Ariel Leonardo VERA VILLARROEL ,  Subramaniam SHANKAR ,  Steffen O. NIELSEN

IPC: H03G3/30 ,  H03F3/45 ,  H03F3/19

CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/083 ,  H03F3/19 ,  H03F3/211 ,  H03F3/4508 ,  H03F3/45085 ,  H03F2200/451 ,  H03F2200/91 ,  H03F2203/45458 ,  H03F2203/45496 ,  H03F2203/45644 ,  H03G1/0023 ,  H03G1/0082 ,  H03G5/28

Abstract: A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a −3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

公开(公告)号：US20170179934A1

公开(公告)日：2017-06-22

申请号：US15451196

申请日：2017-03-06

Applicant: INPHI CORPORATION

Inventor： Travis William LOVITT

IPC: H03K3/012 ,  H03M9/00 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/356113 ,  H03M9/00 ,  H04B1/40 ,  H04L25/03057 ,  H04L25/03146

Abstract: An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

公开(公告)号：US09671581B2

公开(公告)日：2017-06-06

申请号：US15289894

申请日：2016-10-10

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. Nagarajan ,  Peng-Chih Li ,  Masaki Kato

IPC: G02B6/12 ,  H04B10/00 ,  G02B6/42 ,  H04B10/40 ,  H04J14/02 ,  H04B10/516 ,  G02B6/30 ,  G02F1/225 ,  G02F1/21

CPC classification number: G02B6/4257 ,  G02B6/30 ,  G02B6/421 ,  G02B6/4243 ,  G02B6/4246 ,  G02B6/4251 ,  G02B6/4271 ,  G02B6/428 ,  G02B6/4284 ,  G02B6/4286 ,  G02B6/4292 ,  G02F1/2255 ,  G02F2001/212 ,  H04B10/40 ,  H04B10/516 ,  H04J14/02

Abstract: The apparatus includes a case having a base member, two partial side members, and a lid member to provide a spatial volume with an opening at a back end of the base member. Additionally, the apparatus includes a PCB installed inside the spatial volume over the base member with a pluggable connector at the back end. The apparatus includes one or more optical transmitting devices in transmit-optical-sub-assembly package, each being mounted upside-down on the PCB and including a built-in TEC module in contact with the lid member and a laser output port aiming toward the back end. Furthermore, the apparatus includes a silicon photonics chip including a fiber-to-silicon attachment module, mounted on the PCB and coupled to a modulation driver module and a trans-impedance-amplifier module. Moreover, the apparatus includes an optical input port and output port being back connected to the fiber-to-silicon attachment module.

公开(公告)号：US20170141843A1

公开(公告)日：2017-05-18

申请号：US15406230

申请日：2017-01-13

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. NAGARAJAN

IPC: H04B10/071 ,  H04L12/26 ,  H04L12/933 ,  H04Q11/00

CPC classification number: H04B10/071 ,  H04B10/40 ,  H04L43/50 ,  H04L49/109 ,  H04Q11/0005 ,  H04Q2011/0018 ,  H04Q2011/0035

Abstract: In an example, the present invention includes an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

公开(公告)号：US09651751B1

公开(公告)日：2017-05-16

申请号：US15067125

申请日：2016-03-10

Applicant: INPHI CORPORATION

Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan ,  Roberto Coccioli

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122 ,  G02B6/43 ,  G02B6/13 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01S5/022 ,  H04B10/40

CPC classification number: G02B6/4246 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/4245 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12142 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/81 ,  H01L25/167 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/81191 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H04B10/40 ,  H05K1/0274 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2201/10378 ,  H05K2203/049 ,  Y02P70/611 ,  Y02P70/613

Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.

公开(公告)号：US09647825B2

公开(公告)日：2017-05-09

申请号：US14858347

申请日：2015-09-18

Applicant: INPHI CORPORATION

Inventor： Sheldon James Hood ,  Paul Thomas Banens

IPC: H04L7/00 ,  H03K5/135 ,  H04B1/04 ,  H03K5/00

CPC classification number: H04L7/0016 ,  H03K5/133 ,  H03K5/135 ,  H03K19/00361 ,  H03K19/21 ,  H03K2005/00078 ,  H03L7/0807 ,  H04B1/04 ,  H04L25/49

Abstract: When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.

公开(公告)号：US20170127160A1

公开(公告)日：2017-05-04

申请号：US15407150

申请日：2017-01-16

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. NAGARAJAN

IPC: H04Q11/00 ,  H04B10/516 ,  H04B10/54

CPC classification number: H04Q11/0005 ,  H04B10/40 ,  H04B10/5161 ,  H04B10/541 ,  H04Q11/0062 ,  H04Q2011/0016 ,  H04Q2011/0083 ,  H04Q2011/0096

Abstract: In an example, the present invention includes an integrated system on chip device. The device has a variable bias block configured with the control block, the variable bias block being configured to selectively tune each of a plurality of laser devices provided on the silicon photonics device to adjust for at least a wavelength of operation, a fabrication tolerance, and an extinction ratio.

公开(公告)号：US20170126217A1

公开(公告)日：2017-05-04

申请号：US15375048

申请日：2016-12-09

Applicant: INPHI CORPORATION

Inventor： James Lawrence GORECKI ,  Han-Yuan TAN

IPC: H03K5/02 ,  H03M1/12 ,  H04B1/16 ,  H03M1/66 ,  H03M1/38 ,  H03G3/20 ,  H03K3/012 ,  H03F3/45

CPC classification number: H03K5/023 ,  H03F3/3001 ,  H03F3/3033 ,  H03F3/45076 ,  H03F3/45179 ,  H03F3/68 ,  H03G3/20 ,  H03K3/012 ,  H03K5/01 ,  H03K5/02 ,  H03M1/1245 ,  H03M1/38 ,  H03M1/66 ,  H04B1/16

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

公开(公告)号：US09639281B1

公开(公告)日：2017-05-02

申请号：US15267046

申请日：2016-09-15

Applicant: INPHI CORPORATION

Inventor： Aws Shallal ,  Larry Grant Giddens

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10 ,  G06F3/06 ,  G06F1/08 ,  G11C7/08

CPC classification number: G11C14/0018 ,  G06F1/08 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/005 ,  G11C11/4076 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028

Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller. In other embodiments, certain fixed and/or programmable delay elements can be implemented to compensate for various asynchronous delays.

公开(公告)号：US09612457B2

公开(公告)日：2017-04-04

申请号：US15348018

申请日：2016-11-10

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. Nagarajan ,  Hari Shankar ,  Masaki Kato ,  Yang Fu

IPC: G02F1/01 ,  G02F1/225 ,  H04B10/50 ,  G02F1/21 ,  H01S3/067 ,  H01S3/16

CPC classification number: G02F1/0123 ,  G02B6/12007 ,  G02F1/0147 ,  G02F1/025 ,  G02F1/225 ,  G02F1/2255 ,  G02F2001/212 ,  G02F2202/105 ,  H01S3/06754 ,  H01S3/1608 ,  H01S5/0085 ,  H01S5/0687 ,  H01S5/4012 ,  H01S5/4087 ,  H04B10/505 ,  H04B10/50575

Abstract: An integrated optical modulator device. The device can include a driver module coupled to an optical modulator. The optical modulator is characterized by a raised cosine transfer function. This optical modulator can be coupled to a light source and a bias control module, which is configured to apply an off-quadrature bias to the optical modulator. This bias can be accomplished by applying an inverse of the modulator transfer function to the optical modulator in order to minimize a noise variance. This compression function can result in an optimized increased top eye opening for a signal associated with the optical modulator. Furthermore, the optical modulator can be coupled to an EDFA (Erbium Doped Fiber Amplifier) that is coupled to a filter coupled an O/E (Optical-to-Electrical) receiver.