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公开(公告)号:US11024220B2
公开(公告)日:2021-06-01
申请号:US15994987
申请日:2018-05-31
Applicant: Invensas Corporation
Inventor: Liang Wang , Rajesh Katkar , Javier A. Delacruz , Ilyas Mohammed , Belgacem Haba
Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.
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公开(公告)号:US10969593B2
公开(公告)日:2021-04-06
申请号:US17019080
申请日:2020-09-11
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed , Rajesh Katkar
IPC: G02B27/01
Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
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公开(公告)号:US10955671B2
公开(公告)日:2021-03-23
申请号:US16136776
申请日:2018-09-20
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed , Gabriel Z. Guevara , Min Tao
Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.
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公开(公告)号:US20200279821A1
公开(公告)日:2020-09-03
申请号:US16776182
申请日:2020-01-29
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed
IPC: H01L23/00
Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.
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公开(公告)号:US20200035886A1
公开(公告)日:2020-01-30
申请号:US15430428
申请日:2017-02-10
Applicant: Invensas Corporation
Inventor: Ilyas Mohammed , Liang Wang
Abstract: High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.
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公开(公告)号:US10510659B2
公开(公告)日:2019-12-17
申请号:US16202392
申请日:2018-11-28
Applicant: Invensas Corporation
Inventor: Ilyas Mohammed
IPC: H01L23/522 , H05K3/40 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/10 , H01L21/56 , H01L21/768
Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.
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公开(公告)号:US10396041B2
公开(公告)日:2019-08-27
申请号:US15449993
申请日:2017-03-05
Applicant: Invensas Corporation
Inventor: Liang Wang , Ilyas Mohammed , Masud Beroz
IPC: H01L23/00 , H01L33/00 , H01L21/683 , H01L25/00 , H01L27/02 , H01L21/02 , H01L23/544
Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.
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公开(公告)号:US10170412B2
公开(公告)日:2019-01-01
申请号:US15951925
申请日:2018-04-12
Applicant: Invensas Corporation
Inventor: Ilyas Mohammed
IPC: H01L23/522 , H01L25/10 , H01L25/065 , H01L23/00 , H01L23/538 , H01L21/768 , H01L21/56 , H05K3/40
Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.
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公开(公告)号:US09761517B2
公开(公告)日:2017-09-12
申请号:US15477265
申请日:2017-04-03
Applicant: Invensas Corporation
Inventor: Rajesh Katkar , Cyprian Emeka Uzoh , Belgacem Haba , Ilyas Mohammed
IPC: H05K1/09 , H05K1/00 , H05K1/11 , H01L23/498 , H01L23/00 , H01L25/065 , H01L23/538 , H01L23/373 , H01L21/48
CPC classification number: H05K1/0306 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L23/13 , H01L23/3731 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5381 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H05K1/09 , H05K1/112 , H05K1/115 , H05K3/4007 , H05K3/42 , H05K2201/09545 , H05K2201/10378 , H05K2203/0323
Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.
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110.
公开(公告)号:US20170141094A1
公开(公告)日:2017-05-18
申请号:US15419237
申请日:2017-01-30
Applicant: Invensas Corporation
Inventor: Terrence Caskey , Ilyas Mohammed
IPC: H01L25/18 , H01L25/065 , H01L21/683 , H01L25/00 , H01L21/56 , H01L23/31 , H01L23/00
CPC classification number: H01L25/18 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/3107 , H01L23/3114 , H01L23/3185 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05554 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/14131 , H01L2224/27334 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/83192 , H01L2224/852 , H01L2224/92144 , H01L2224/92147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1076 , H01L2225/1082 , H01L2924/00014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18162 , H01L2924/186 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
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