公开(公告)号：US20180277530A1

公开(公告)日：2018-09-27

申请号：US15990626

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/00 ,  H01L21/304 ,  H01L25/18 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/7806 ,  H01L25/18

Abstract: A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.

公开(公告)号：US10043781B2

公开(公告)日：2018-08-07

申请号：US15904377

申请日：2018-02-25

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/367 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

公开(公告)号：US09953925B2

公开(公告)日：2018-04-24

申请号：US14975830

申请日：2015-12-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/544 ,  B82Y10/00 ,  G11C16/04 ,  G11C16/10 ,  H01L21/84 ,  H01L21/683 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/10 ,  G11C11/41 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L23/00 ,  H01L29/66 ,  H01L27/088 ,  H01L23/36

CPC classification number: H01L23/5286 ,  B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/36 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

公开(公告)号：US20180047707A1

公开(公告)日：2018-02-15

申请号：US15721955

申请日：2017-10-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5225 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351

Abstract: An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.

公开(公告)号：US09892972B2

公开(公告)日：2018-02-13

申请号：US15201430

申请日：2016-07-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L45/00 ,  H01L27/115 ,  H01L27/06 ,  H01L27/088 ,  H01L27/24 ,  H01L27/11 ,  H01L27/108 ,  H01L23/367 ,  H01L27/22 ,  H01L21/762 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/085 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L23/367 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/226 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/42392 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.

公开(公告)号：US20180033881A1

公开(公告)日：2018-02-01

申请号：US15727592

申请日：2017-10-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L29/78 ,  G11C11/4097 ,  H01L27/24 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  G11C11/404 ,  G11C16/02

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells.

公开(公告)号：US09818800B2

公开(公告)日：2017-11-14

申请号：US14555494

申请日：2014-11-26

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L29/06 ,  H01L27/118 ,  H01L27/24 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/12 ,  H01L27/22 ,  H01L29/78 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11573 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

公开(公告)号：US20170229174A1

公开(公告)日：2017-08-10

申请号：US15494525

申请日：2017-04-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G11C13/00 ,  H01L45/00 ,  H01L29/04 ,  G11C29/00 ,  H01L27/24 ,  H01L29/161

CPC classification number: G11C13/0069 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C16/0483 ,  G11C29/78 ,  G11C2013/0076 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

公开(公告)号：US20170213821A1

公开(公告)日：2017-07-27

申请号：US15482787

申请日：2017-04-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L27/108 ,  H01L29/161 ,  H01L29/78 ,  G11C5/14 ,  H01L21/8234 ,  H01L21/683 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L23/552 ,  H01L23/367 ,  H01L27/24 ,  G11C5/02 ,  H01L27/02

CPC classification number: H01L27/0688 ,  G11C5/02 ,  G11C5/145 ,  G11C5/147 ,  H01L21/48 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/367 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/552 ,  H01L27/0222 ,  H01L27/0251 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/10823 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/48091 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3025 ,  H01L2224/45099

Abstract: A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits

公开(公告)号：US20170207214A1

公开(公告)日：2017-07-20

申请号：US15477106

申请日：2017-04-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L25/11 ,  H01L25/07

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L23/544 ,  H01L25/071 ,  H01L25/117 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L2221/68368 ,  H01L2223/54426 ,  H01L2224/18

Abstract: A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die.