公开(公告)号：US20180012770A1

公开(公告)日：2018-01-11

申请号：US15712373

申请日：2017-09-22

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE ,  Greg P. KLOWAK ,  Howard TWEDDLE

IPC: H01L21/306 ,  H01L21/02 ,  C01G15/00 ,  H05B33/08

CPC classification number: H01L21/30612 ,  C01B21/0632 ,  C01G15/00 ,  H01L21/02507 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/562 ,  H01L23/585 ,  H01L29/2003 ,  H01L29/778 ,  H05B33/0803

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US09824949B2

公开(公告)日：2017-11-21

申请号：US15197861

申请日：2016-06-30

Applicant: GaN Systems Inc.

Inventor： Cameron McKnight-MacNeil ,  Greg P. Klowak ,  Ahmad Mizan ,  Stephen Coates

IPC: H01L23/495 ,  H01L29/78 ,  H01L23/31 ,  H01L29/20 ,  H01L21/78 ,  H01L23/492 ,  H01L21/56 ,  H01L23/00 ,  H01L23/482 ,  H01L21/48

CPC classification number: H01L23/3114 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/7816 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

公开(公告)号：US09659854B2

公开(公告)日：2017-05-23

申请号：US15027012

申请日：2015-04-15

Applicant: GaN Systems Inc.

Inventor： Greg P. Klowak ,  Ahmad Mizan ,  John Roberts

IPC: H01L29/66 ,  H01L29/15 ,  H01L31/02 ,  H01L29/78 ,  H01L23/498 ,  H01L23/482 ,  H01L29/20 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L29/778

CPC classification number: H01L23/49844 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/19 ,  H01L24/20 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/78 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/82

Abstract: Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

公开(公告)号：US09525413B2

公开(公告)日：2016-12-20

申请号：US15099459

申请日：2016-04-14

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Iain H. Scott

IPC: H03K3/00 ,  H03K17/687 ,  H01L29/778 ,  H01L29/20 ,  H03K5/08

CPC classification number: H03K17/687 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/7787 ,  H03K5/08 ,  H03K17/04123 ,  H03K2217/0036

Abstract: Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. In operation, D1 provides the gate drive voltage to the gate of the GaN switch D3, and D2 clamps the gate of the GaN switch D3 to the source, via an internal source-sense connection closely coupling the source of D3 and the source of D2. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

Abstract translation: 公开了包括具有低阈值电压的增强模式（E模式）GaN功率晶体管的开关系统的驱动电路。 E模式高电子迁移率晶体管（HEMT）D3具有单片集成的GaN驱动器，其包括更小的E型GaN HEMT D1和D2以及分立的双电压预驱动器。 在操作中，D1将栅极驱动电压提供给GaN开关D3的栅极，并且D2通过紧密耦合D3源和D2源的内部源极检测连接将GaN开关D3的栅极钳位到源极 。 为前置驱动程序提供了额外的源感测连接。 将D1和D3的驱动电压提升到D1的栅极，可以实现更快速的D1和D3上拉，从而提高开关速度下的开关性能。 驱动器电路的大电流处理部件与GaN开关集成，并且紧密耦合以减小电感，而离散预驱动器可以与GaN芯片热分离。

公开(公告)号：US20160307826A1

公开(公告)日：2016-10-20

申请号：US15197861

申请日：2016-06-30

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Greg P. KLOWAK ,  Ahmad MIZAN ,  Stephen COATES

IPC: H01L23/495 ,  H01L29/78 ,  H01L23/31 ,  H01L29/20

CPC classification number: H01L23/3114 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/7816 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的封装解决方案，包括封装组件的部件，半导体器件结构及其制造方法。 在封装组件中，包括一个或多个横向GaN功率晶体管的GaN管芯被夹在第一和第二引线框层之间，并且使用低电感互连互连，而无需引线接合。 为了散热，双引线框封装组件可以配置为正面或背面冷却。 优选的实施例有利于用于横向GaN器件的高电流/低电感互连的对准和配准，其中用于源极，漏极和栅极接触的接触区域或焊盘设置在GaN管芯的前侧。 通过消除引线键合，并且使用具有高导电和导热性的低电感互连，PQFN技术可以适用于封装包含一个或多个横向GaN功率晶体管的GaN晶体管。

公开(公告)号：US20160301408A1

公开(公告)日：2016-10-13

申请号：US15091867

申请日：2016-04-06

Applicant: GaN Systems Inc.

Inventor： John ROBERTS ,  Ahmad MIZAN

IPC: H03K17/687 ,  H01L29/20

CPC classification number: H03K17/162 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H03K17/168 ,  H03K17/6877

Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

Abstract translation: 公开了包括具有低阈值电压的增强型（E模））GaN功率晶体管的驱动电路的电源开关系统。 优选地，GaN功率开关（D3）包括具有单片集成GaN驱动器的E模式高电子迁移率晶体管（HEMT）。 D3被划分为几个部分。 至少下拉和可选地，上拉驱动器电路被类似地划分为多个驱动器元件，每个驱动器元件驱动D3的相应部分。 每个驱动器元件放置在D3的相应部分附近，减少了互连轨道长度和环路电感。 在优选实施例中，选择GaN晶体管开关的布局和驱动元件，互连轨道的尺寸和布线，以进一步降低环路电感并优化性能。 集成片上与一个或多个高功率E-Mode GaN开关的分布式驱动器电路允许驱动电路和GaN开关的更紧密耦合，以减少寄生电感的影响。

公开(公告)号：US20160268190A1

公开(公告)日：2016-09-15

申请号：US15064750

申请日：2016-03-09

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Greg P. KLOWAK ,  Ahmad MIZAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

Abstract: Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

Abstract translation: 公开了用于大面积的包括一个或多个横向GaN功率晶体管器件和系统的GaN管芯的封装解决方案。 包装组件包括包括横向GaN管芯和引线框架的插入件子组件。 GaN管芯使用凸点或柱互连，银烧结或其他低电感互连电连接到引线框架。 然后，在单个工艺步骤中制造GaN管芯到衬底的连接以及引线框架与衬底上的触点的电连接。 子组件可以安装在标准功率模块中，或者替代地安装在诸如印刷电路板的基板上。 对于高电流应用，子组件还包括用于散热的陶瓷衬底。 与传统的引线键合功率模块相比，该封装方案提供了具有较低电感和较高电流容量的互连，简化了制造，并且能够改进组件的热匹配。

公开(公告)号：US20160240471A1

公开(公告)日：2016-08-18

申请号：US15027012

申请日：2015-04-15

Applicant: GaN Systems Inc.

Inventor： Greg P. KLOWAK ,  Ahmad MIZAN ,  John ROBERTS

IPC: H01L23/498 ,  H01L23/522 ,  H01L29/20 ,  H01L23/532 ,  H01L29/78 ,  H01L23/482

CPC classification number: H01L23/49844 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/19 ,  H01L24/20 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/78 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/82

Abstract: Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的嵌入式封装。 包装组件适用于大面积高功率GaN晶体管，并且包括GaN功率晶体管和包括三级互连结构的封装组件的组件。 在优选实施例中，三电平互连结构包括片上金属层，铜再分布层和封装金属层，其中存在通过三个级别分级/施加电流片上的刻度或锥形接触面积， 在GaN功率器件的有源区域上结合/收集芯片外的电流与分布式触点。 该嵌入式封装组件提供适合于用于高电压/高电流应用的大面积高功率GaN晶体管的器件和系统的低电感，低电阻互连结构。

公开(公告)号：US20150318851A1

公开(公告)日：2015-11-05

申请号：US14654127

申请日：2013-12-12

Applicant: GAN SYSTEMS INC.

Inventor： John ROBERTS ,  Greg P. KLOWAK

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H01F19/08 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/1204 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Abstract translation: 公开了一种包括用于功率晶体管的驱动电路的电子开关系统和装置，其特别适用于MOSFET驱动的常规氮化镓（GaN）功率晶体管。 优选地，具有集成的低电压横向MOSFET驱动器的低功率，高速CMOS驱动器电路以混合共源共栅布置串联耦合到高电压GaN HEMT，并且提供对噪声和电压瞬变的改进的控制。 监控和控制功能，包括闭锁和钳位，都是基于对关闭和启动调节的Vcc条件进行监控，以实现更安全的操作，特别是对于高电压和高电流开关。 优选实施例还提供具有减小的输入损耗的隔离，自供电的高速驱动器件。