公开(公告)号：US09831287B2

公开(公告)日：2017-11-28

申请号：US15277551

申请日：2016-09-27

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: G11C5/02 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  G11C11/34 ,  H01L29/66

CPC classification number: H01L27/2418 ,  G11C5/02 ,  G11C11/34 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/003 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2216/08 ,  H01L29/6609 ,  H01L45/00 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

公开(公告)号：US09640260B2

公开(公告)日：2017-05-02

申请号：US14320174

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66 ,  G11C16/04 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/792 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US09614006B2

公开(公告)日：2017-04-04

申请号：US14865806

申请日：2015-09-25

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/24 ,  H01L27/102 ,  G11C13/00 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L21/768 ,  H01L23/528 ,  H01L24/80 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1608 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.

公开(公告)号：US09559194B2

公开(公告)日：2017-01-31

申请号：US15003679

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L21/02 ,  H01L27/115 ,  H01L29/12 ,  H01L29/786

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫属化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。

公开(公告)号：US09559118B2

公开(公告)日：2017-01-31

申请号：US15095211

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

Abstract translation: 垂直铁电场效应晶体管结构包括隔离芯。 过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。 铁电栅极电介质材料围绕过渡金属二硫属元素材料。 导电栅极材料围绕铁电栅极电介质材料。 过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。 导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。 公开了另外的实施例。

公开(公告)号：US20160155829A1

公开(公告)日：2016-06-02

申请号：US15003679

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫族化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。

公开(公告)号：US09276134B2

公开(公告)日：2016-03-01

申请号：US14519021

申请日：2014-10-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115 ,  H01L29/06 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

Abstract translation: 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿着底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料的厚度在大于约至小于或等于的范围内; 和/或具有1个单层至7个单层的厚度。

公开(公告)号：US09202871B2

公开(公告)日：2015-12-01

申请号：US14275847

申请日：2014-05-12

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L29/16 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66 ,  H01L29/808 ,  H01L29/812

CPC classification number: H01L29/1608 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66848 ,  H01L29/66916 ,  H01L29/808 ,  H01L29/812 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

Abstract: Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.

Abstract translation: 提供了提供具有改进的操作特性的晶体管的装置。 在一个示例中，系统包括处理器和存储器设备。 处理器或存储器件的晶体管包括半导体衬底中的未掺杂或固有的沟道。 金属栅极直接设置在通道的顶部，半导体衬底的带隙和金属的功函形成肖特基势垒。

公开(公告)号：US09159375B2

公开(公告)日：2015-10-13

申请号：US14628123

申请日：2015-02-20

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L29/861 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L27/2463 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L21/768 ,  H01L23/528 ,  H01L24/80 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1608 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.

Abstract translation: 一些实施例包括在第一和第二电极之间选择性地导电具有第一电极，第二电极和介电材料的器件。 电介质材料可以被配置为当跨越第一电极和第二电极施加第一电压时，将电流从第一电极传导到第二电极。 此外，当具有与第一电压的极性相反的极性的第二电压跨越第一电极和第二电极施加的第二电压时，电介质材料可以被配置为抑制电流从第二电极流到第一电极。 二极管材料可以包括按照增加势垒高度的顺序布置的多个不同介电材料层。 响应于第一电压，量子阱可以在多个层的结的处形成。 一些实施例包括二极管形成方法。

公开(公告)号：US20150200202A1

公开(公告)日：2015-07-16

申请号：US14152664

申请日：2014-01-10

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66666

Abstract: A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed.

Abstract translation: 场效应晶体管结构包括两个源极/漏极区域和其间的沟道区域。 通道区域包含厚度为1单层至7层的过渡金属二硫属元素材料，并且在源极/漏极区域之间具有物理长度。 中间栅极相对于物理长度可操作地邻近沟道区的中部。 一对门可操作地接近沟道区域与中栅极接近的沟道区域的部分的不同相应部分。 一对门与中门对面的中间门隔开并与之隔离。 栅极电介质位于a）沟道区域之间，b）中间栅极与栅极对之间。 公开了另外的实施例。