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    LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER
    115.
    发明申请
    LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER 有权
    低延迟，频率 - 时钟时钟乘法器

    公开(公告)号：US20150091617A1

    公开(公告)日：2015-04-02

    申请号：US14565802

    申请日：2014-12-10

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

    IPC: H03K5/13 ,  H03L7/16 ,  H03K5/00

    CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

    Abstract translation: 在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。 在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。 在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。 响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择 时钟。

    METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING
    116.
    发明申请
    METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING 有权
    用于同源信号的方法和装置

    公开(公告)号：US20140347108A1

    公开(公告)日：2014-11-27

    申请号：US14456716

    申请日：2014-08-11

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

    IPC: H03L7/091 ,  H03L7/099 ,  H03L7/08

    CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

    Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

    Abstract translation: 在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。 芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

    CROSSTALK REDUCTION CODING SCHEMES
    117.
    发明申请
    CROSSTALK REDUCTION CODING SCHEMES 有权
    减速器编码方案

    公开(公告)号：US20140023161A1

    公开(公告)日：2014-01-23

    申请号：US13937549

    申请日：2013-07-09

    Applicant: Rambus Inc.

    Inventor： Reza Navid ,  Amir Amirkhany ,  Dinesh D. Patil ,  Brian S. Leibowitz

    IPC: H04L1/00

    CPC classification number: H04L1/0083 ,  H04L1/0001 ,  H04L1/0002 ,  H04L1/0007

    Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.

    Abstract translation: 数据编码方案执行基于电平和/或基于转换的编码，以避免在通过并行通信链路将多位数据从一个电路传输到另一电路时产生最差情况串扰的信令条件。 编码方案不允许某些模式存在于信号电平，信号转换或信号电平和信号转换的组合中，信号电平和信号转换发生在对应于并行通信链路的某些物理相邻电线的多位数据的子集中 。

    EDGE BASED PARTIAL RESPONSE EQUALIZATION
    118.
    发明申请
    EDGE BASED PARTIAL RESPONSE EQUALIZATION 有权
    基于边缘部分响应均衡

    公开(公告)号：US20140016692A1

    公开(公告)日：2014-01-16

    申请号：US13932561

    申请日：2013-07-01

    Applicant: Rambus Inc.

    Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    IPC: H04L25/03

    CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

    Abstract: A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

    Abstract translation: 设备实现基于边缘的部分响应判决反馈均衡的数据接收。 在一个示例性实施例中，该设备实现一个抽头权重适配器电路，其设置用于调整接收到的数据信号的抽头权重。 抽头重量适配器电路基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样的数据信号。 时钟发生电路产生边沿时钟信号，以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

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