公开(公告)号：US09666560B1

公开(公告)日：2017-05-30

申请号：US14951892

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Guilian Gao ,  Hong Shen ,  Rajesh Katkar ,  Belgacem Haba

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L25/0655 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/116 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a planarized encapsulation. A circuit structure having a thickness less than or equal to 10 microns, formed by depositing two or more dielectric layers and conductive layers on the respective dielectric layers, has electrically conductive features thereon which electrically contact the bumps. The circuit structure can be formed separately on a carrier and then joined with the bumps on the dielectric element, or the circuit structure can be formed by a build up process on the planarized surface of the encapsulation and the planarized surfaces of the bumps.

公开(公告)号：US20170148763A1

公开(公告)日：2017-05-25

申请号：US14952482

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/3107 ,  H01L24/02 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

公开(公告)号：US09502347B2

公开(公告)日：2016-11-22

申请号：US14629271

申请日：2015-02-23

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Arkalgud R. Sitaram

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Abstract translation: 两个微电子部件（110,120），例如 模具和插入件彼此结合。 部件的接触焊盘（110C）中的一个包括金属，另一部件具有与金属反应形成金属硅化物（504）的硅（410）。 然后通过其中一个部件制成一个孔（510），以到达金属硅化物，甚至可能连接另一部件的未反应的金属（110C）。 该孔填充有可能是金属的导体（130），以提供可电耦合到可附接到其它电路元件或微电子部件的接触焊盘（120C.B）的导电通孔，例如。 到印刷电路板。

公开(公告)号：US09356006B2

公开(公告)日：2016-05-31

申请号：US14953565

申请日：2015-11-30

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Liang Wang

IPC: H01L21/44 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15333 ,  H01L2924/014 ,  H01L2924/00

Abstract: A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.

公开(公告)号：US09324626B2

公开(公告)日：2016-04-26

申请号：US14558462

申请日：2014-12-02

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/31 ,  H01L21/288 ,  H01L21/56 ,  H01L21/768 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 623) connect the dies to the cavity's bottom all (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

Abstract translation: 堆叠的管芯（110）通过由可模制材料形成的多个密封层（524）封装在插入件的空腔（304）中。 导电路径（520,623）将模具连接到空腔的底部（304B），并且通过穿过底壁的TSV连接到插入件下方的导体。 导电路径可以形成为各自形成在各个密封层中的通孔（514）中的段。 每个段可以通过电镀形成在下段上; 电镀电流可以通过TSV和较早形成的片段从插入件的下方提供。 还提供其他功能。

公开(公告)号：US09214454B2

公开(公告)日：2015-12-15

申请号：US14230388

申请日：2014-03-31

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Liang Wang

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15333 ,  H01L2924/014 ,  H01L2924/00

Abstract: A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.

Abstract translation: 微电子组件可以通过用导电块连接第一和第二子组件来连接每个子组件的支撑元件上的导电元件来制造。 可光成像材料的图案层可以覆盖在一个支撑元件的表面上，并且具有开口，其横截面尺寸与该支撑元件的表面的高度不变或单调地增加，其中质量延伸穿过开口和 具有由此定义的尺寸。 可以通过将密封剂流入连接的第一和第二子组件之间的空间来形成封装。

公开(公告)号：US09165793B1

公开(公告)日：2015-10-20

申请号：US14268899

申请日：2014-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/00 ,  H01L21/56

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Abstract translation: 制造集成电路封装的方法包括提供具有限定空腔的第一区域的处理晶片。 在第一区域形成电容器。 电容器具有一对电极，每对电极耦合到一对导电焊盘中的一个，其至少一个设置在处理晶片的下表面上。 还提供了具有上表面的插入件，其具有导电焊盘和设置在其上的至少一个半导体管芯。 芯片具有与内插器的再分配层（RDL）电导耦合的集成电路。 把手晶片的下表面被结合到插入件的上表面，使得模具设置在空腔的下方或内部，并且处理晶片的导电焊盘以金属间隔结合到插入件的导电焊盘上， 金属键。

公开(公告)号：US20150263252A1

公开(公告)日：2015-09-17

申请号：US14727810

申请日：2015-06-01

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Masud Beroz ,  Ilyas Mohammed

IPC: H01L33/58 ,  H01L51/52 ,  H01L33/44

CPC classification number: H01L33/58 ,  H01L33/44 ,  H01L51/5262 ,  H01L51/5268 ,  H01L51/5275 ,  H01L2251/5369 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: Optical enhancement of light emitting devices. In accordance with an embodiment of the present invention, an apparatus includes an optical enhancement layer comprising nanoparticles. Each of the nanoparticles includes an electrically conductive core surrounded by an electrically insulating shell. The optical enhancement layer is disposed on a top semiconductor layer in a preferred path of optical emission of a light emitting device. The nanoparticles may enhance the light emission of the light emitting device due to emitter-surface plasmon coupling.

Abstract translation: 发光器件的光学增强。 根据本发明的实施例，一种装置包括包含纳米颗粒的光学增强层。 每个纳米颗粒包括由电绝缘壳包围的导电芯。 光学增强层设置在发光器件的光发射的优选路径中的顶部半导体层上。 纳米颗粒可以由于发射体 - 表面等离子体耦合而增强发光器件的发光。

公开(公告)号：US20150262928A1

公开(公告)日：2015-09-17

申请号：US14558462

申请日：2014-12-02

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/288 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 623) connect the dies to the cavity's bottom all (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

Abstract translation: 堆叠的管芯（110）通过由可模制材料形成的多个密封层（524）封装在插入件的空腔（304）中。 导电路径（520,623）将模具连接到空腔的底部（304B），并且通过穿过底壁的TSV连接到插入件下方的导体。 导电路径可以形成为各自形成在各个密封层中的通孔（514）中的段。 每个段可以通过电镀形成在下段上; 电镀电流可以通过TSV和较早形成的片段从插入件的下方提供。 还提供其他功能。

公开(公告)号：US20150171027A1

公开(公告)日：2015-06-18

申请号：US14466992

申请日：2014-08-23

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

IPC: H01L23/00 ,  H01L27/02

CPC classification number: H01L23/562 ,  H01L21/02002 ,  H01L21/02035 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02414 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0207 ,  H01L33/005 ,  H01L33/0062 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Abstract translation: 高产量基板组件。 根据第一方法实施例，将多个搭载基板附接到载体基板。 多个搭载基板的边缘彼此接合。 将多个搭载基板从载体基板上移除以形成基板组件。 处理衬底组件以在衬底组件上产生多个集成电路器件。 处理可以使用设计成处理大于多个背负式基板的单独实例的晶片的制造设备。