公开(公告)号：US20150378818A1

公开(公告)日：2015-12-31

申请号：US14828013

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract translation: 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

公开(公告)号：US20150347223A1

公开(公告)日：2015-12-03

申请号：US14823804

申请日：2015-08-11

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

公开(公告)号：US09196348B2

公开(公告)日：2015-11-24

申请号：US14613282

申请日：2015-02-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F13/00 ,  G11C11/406 ,  G06F13/16 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US09165639B2

公开(公告)日：2015-10-20

申请号：US14538524

申请日：2014-11-11

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G06F3/00 ,  G11C11/4093 ,  G11C5/04 ,  G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20150243342A1

公开(公告)日：2015-08-27

申请号：US14669919

申请日：2015-03-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/409 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract translation: 存储器系统包括将数据写入存储器件并从存储器件读取数据的存储器控​​制器。 伴随写入数据的写入数据选通信号在写入数据有效时向存储器件指示，而伴随来自存储器件的数据的读取选通器在读取数据有效时向存储器控制器指示。 存储器控制器自适应地控制写入数据选通的相位以补偿存储器件的定时漂移。 存储器控制器使用读取信号作为漂移的度量。

公开(公告)号：US20150234754A1

公开(公告)日：2015-08-20

申请号：US14702995

申请日：2015-05-04

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10

CPC classification number: G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

Abstract: Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data over the respective subset of data lines. The memory modules can be width configurable so that a single full-width module can connect to both subsets of data lines to convey full-width data, or two half-width modules can connect one each to the subsets of data lines.

Abstract translation: 描述的是其中存储器控制器向共同支持每个读取和写入事务的多个存储器模块发出命令和地址的存储器系统。 来自控制器的一组共同的控制信号线将相同的命令和地址信号传送给模块。 对于写命令，控制器通过数据线的相应子集向每个模块发送写数据子集。 对于读取命令，每个模块通过数据线的相应子集来响应所请求数据的子集。 存储器模块可以宽度可配置，使得单个全宽度模块可以连接到数据线的两个子集以传送全宽数据，或者两个半宽度模块可以将每个数据线连接到数据线的子集。

公开(公告)号：US09087568B1

公开(公告)日：2015-07-21

申请号：US13848832

申请日：2013-03-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C8/00 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1039 ,  G11C7/222 ,  G11C11/40615 ,  G11C11/4076

Abstract: Chip selection and internal clocking functions are enabled within an integrated circuit memory component in response to a single “chip-enable” control signal, thus reducing memory system pin count and wiring complexity relative to designs that require separate chip-select and clock-enable signals. Internal clocking logic may also be provided to generate timing signal edges more precisely limited to the number required to complete a given memory component operation, reducing the number of unnecessary timing events and lowering power consumption. Further, internal read and write clock signals may be speculatively enabled within the memory component to more quickly stabilize those clocks in preparation for data transmission and reception operations, potentially lowering memory access latency.

Abstract translation: 芯片选择和内部时钟功能在集成电路存储器组件内响应于单个“芯片使能”控制信号而被使能，从而相对于需要单独的芯片选择和时钟使能信号的设计而减少存储器系统引脚数量和布线复杂度 。 还可以提供内部时钟逻辑以产生更精确地限制完成给定存储器组件操作所需的数量的定时信号边沿，减少不必要的定时事件的数量并降低功耗。 此外，内部读和写时钟信号可以在存储器组件内被推测启用，以更快地稳定这些时钟以准备数据传输和接收操作，潜在地降低存储器访问等待时间。

公开(公告)号：US20150162101A1

公开(公告)日：2015-06-11

申请号：US14407318

申请日：2013-10-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ian Shaeffer

IPC: G11C29/44 ,  G06F11/10

CPC classification number: G11C29/4401 ,  G06F11/1016 ,  G06F11/1072 ,  G11C29/808 ,  G11C29/846

Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

Abstract translation: 存储器设备（100）包括修复存储器块的额外列（114）。 这些修复存储器瓦片同时被以与主阵列的存储器瓦片相同的方式被访问。 修复列的输出代替主阵列（112）的列的输出。 取代的主阵列列由存储在外部的存储器件的标签（121）决定。 使用访问的部分地址查询外部标记。 如果访问的地址对应于外部标签中的地址，则将标签信息提供给存储设备。 标签信息确定主阵列中的哪个列由修复列的输出替代。 由于主阵列的每列在访问期间提供一位，所以修复列可以逐个单元替换主阵列单元。

公开(公告)号：US20150074437A1

公开(公告)日：2015-03-12

申请号：US14546687

申请日：2014-11-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/12 ,  G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract translation: 集成电路存储器控制器向存储器件输出处于第一状态的第一信号，以使存储器件内的同步数据发送和接收电路能够操作。 存储器控制器内的事务队列存储要被服务的存储器读和写请求，分别要求存储器件内的同步数据发送和接收电路的操作。 存储器控制器内的电源控制电路确定事务队列已经达到预定状态，并且作为响应，在第二状态下将第一信号输出到存储器件，以禁止存储器件内的同步数据发送和接收电路的操作。

公开(公告)号：US20140351673A1

公开(公告)日：2014-11-27

申请号：US14285467

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Brent Haukness ,  Scott C. Best ,  Wayne F. Ellis

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1092 ,  G06F2211/1092 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.

Abstract translation: 公开了一种存储器件，其包括用于存储数据字的存储位置行和备用行元件。 数据字通过用于产生用于校正X位错误的错误信息的错误代码进行编码，或者检测Y位错误，其中Y大于X.备用行元件具有替代的存储位置。 逻辑响应于检测到的错误，以（1）能够基于错误信息来校正数据字，其中存在不超过X位错误，以及（2）将备用行元素替换为存在行的一部分 数据字中至少有Y位错误。