公开(公告)号：US09576839B2

公开(公告)日：2017-02-21

申请号：US14383520

申请日：2013-02-20

申请人： OSRAM Opto Semiconductors GmbH

发明人： Thomas Bauer

IPC分类号： H01L21/687 ,  B05C13/02 ,  H01L21/02 ,  C23C16/458 ,  H01L21/67

CPC分类号： H01L21/68742 ,  B05C13/02 ,  C23C16/458 ,  H01L21/02365 ,  H01L21/67109

摘要： A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.

摘要翻译： 提供了一种用于涂层系统（12）的衬底载体布置（10,11），其包括载体（1），所述载体（1）包括至少一个具有支撑表面（30）的支撑区域（3），衬底支撑件 ），并且所述支撑区域在所述支撑表面（30）中包括至少一个第一和第二气体入口（4,5），其中所述第一气体入口（4）距离中心（M）更小的距离， 所述第一和第二气体入口（4,5）包括彼此独立的气体进料（40,50），所述气体进料被配置成供应具有相互不同热导率的气体。 还提供了一种包括基板载体装置和用于执行涂布工艺的方法的涂覆系统。

公开(公告)号：US20160322391A1

公开(公告)日：2016-11-03

申请号：US15210420

申请日：2016-07-14

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/20 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

摘要： A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

公开(公告)号：US09368579B2

公开(公告)日：2016-06-14

申请号：US13762140

申请日：2013-02-07

申请人： The Board of Trustees of the Leland Stanford Junior University

发明人： Krishna Coimbatore Balram ,  Stephanie A. Claussen ,  David A. B. Miller

IPC分类号： H01L29/12 ,  H01L21/02 ,  H01L29/20

CPC分类号： H01L29/12 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/20

摘要： A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a spacer layer which covers the sidewalls. Undesirable exposure of the top corners of the growth windows is prevented by undercutting the growth window prior to deposition of the dielectric spacer layer. The effectiveness of this process has been demonstrated by selective-area growth of Ge and Ge/SiGe quantum wells on a silicon substrate. Integration of active optoelectronic devices with waveguide layers via end-coupling through the dielectric spacer layer can be reliably accomplished in this manner.

摘要翻译： 提供了一种用于增长窗口中半导体选择性面积增长的强大制造工艺。 通过存在覆盖侧壁的间隔层来消除侧壁生长。 通过在沉积介电隔离层之前削弱生长窗口来防止生长窗的顶角的不期望的暴露。 通过在硅衬底上的Ge和Ge / SiGe量子阱的选择性区域生长证明了该过程的有效性。 以这种方式可以可靠地实现通过端接耦合将有源光电子器件与波导层集成通过电介质间隔层。

公开(公告)号：US20160035567A1

公开(公告)日：2016-02-04

申请号：US14878399

申请日：2015-10-08

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L29/7869 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/30604 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3248 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78693 ,  H01L29/78696

摘要： A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

公开(公告)号：US09236251B2

公开(公告)日：2016-01-12

申请号：US14705425

申请日：2015-05-06

申请人： GLOBALFOUNDRIES INC.

发明人： Can Bayram ,  Cheng-Wei Cheng ,  Tak H. Ning ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC分类号： H01L21/02 ,  H01L29/267 ,  H01L29/06

CPC分类号： H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/2007 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/267

摘要： Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.

公开(公告)号：US09184338B2

公开(公告)日：2015-11-10

申请号：US14347443

申请日：2011-09-28

申请人： Meoung Whan Cho ,  Seog Woo Lee ,  Ryuichi Toba ,  Yoshitaka Kadowaki

发明人： Meoung Whan Cho ,  Seog Woo Lee ,  Ryuichi Toba ,  Yoshitaka Kadowaki

IPC分类号： H01L21/00 ,  H01L33/00 ,  H01L21/02 ,  H01L21/78 ,  H01L29/06 ,  H01L33/20

CPC分类号： H01L33/0075 ,  H01L21/02365 ,  H01L21/78 ,  H01L29/0603 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/20

摘要： The method of manufacturing a semiconductor device according to the present invention includes: a step of forming a semiconductor laminate on a growth substrate with a lift-off layer therebetween; a step of providing grooves in a grid pattern in the semiconductor laminate, thereby forming a plurality of semiconductor structures each having a nearly quadrangular transverse cross-sectional shape; a step of forming a conductive support body; and a step of removing the lift-off layer using a chemical lift-off process, in which step, in supplying an etchant to the grooves via through-holes provided in a portion above the grooves, the lift-off layer is etched from only one side surface of each semiconductor structure.

摘要翻译： 根据本发明的制造半导体器件的方法包括：在其上具有剥离层的生长衬底上形成半导体层叠体的步骤; 在半导体层叠体中设置栅格图案的沟槽的步骤，由此形成多个具有近似四边形横截面形状的半导体结构; 形成导电性支撑体的工序; 以及使用化学剥离处理去除剥离层的步骤，其中通过设置在沟槽上方的通孔的沟槽向槽施加蚀刻剂，仅剥离层仅从蚀刻 每个半导体结构的一个侧表面。

公开(公告)号：US20150270404A1

公开(公告)日：2015-09-24

申请号：US14733489

申请日：2015-06-08

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC分类号： H01L29/786 ,  H01L29/04 ,  G02F1/1362 ,  H01L27/12 ,  H01L27/32 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/423

CPC分类号： H01L29/7869 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/30604 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3248 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78693 ,  H01L29/78696

摘要： A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

摘要翻译： 晶体管包括层叠有氧化物半导体膜和氧化膜的多层膜，栅极电极和栅极绝缘膜。 多层膜与栅电极重叠，栅极绝缘膜介于其间。 多层膜具有在氧化物半导体膜的底面和氧化物半导体膜的侧面之间具有第一角度的形状，以及氧化物膜的底面与氧化膜的侧面之间的第二角度。 第一个角度是锐角并小于第二个角度。 此外，制造包括这种晶体管的半导体器件。

公开(公告)号：US09099303B2

公开(公告)日：2015-08-04

申请号：US14208280

申请日：2014-03-13

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/477 ,  H01L21/265 ,  H01L29/786 ,  H01L29/66 ,  H01L21/77

CPC分类号： H01L21/02323 ,  H01L21/02365 ,  H01L21/02554 ,  H01L21/02631 ,  H01L21/02664 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/477 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2021/775

摘要： Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction.

摘要翻译： 氧化物半导体膜中的氧空位和氧化物半导体膜附近的氧空位减小，并且包括氧化物半导体膜的晶体管的电特性得到改善。 此外，提供了包括包括氧化物半导体膜的晶体管的高度可靠的半导体器件。 在包括氧化物半导体膜的晶体管中，与氧化物半导体膜接触的至少一个绝缘膜含有过量的氧。 通过与氧化物半导体膜接触的绝缘膜中包含的过量的氧，可以减少氧化物半导体膜中的氧空位和氧化物半导体膜附近的氧空位。 注意，包括过量氧的绝缘膜具有在深度方向上具有两个或更多个局部最大值的过量氧浓度的分布。

公开(公告)号：US09054024B2

公开(公告)日：2015-06-09

申请号：US13372246

申请日：2012-02-13

申请人： Fei Yu ,  Qi Deng

发明人： Fei Yu ,  Qi Deng

IPC分类号： H01L21/00 ,  H01L25/16 ,  H01L21/02 ,  G02B6/42

CPC分类号： H01L25/167 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/428 ,  H01L21/02365 ,  H01L2224/16

摘要： An integrated circuit package includes a substrate having a recess formed along at least a portion of a perimeter of the substrate, and an optical die having opto-electric circuitry, the optical die coupled to the substrate such that a portion of the optical die with the opto-electric circuitry overhangs the recess. The integrated circuit package also includes an optical unit disposed in the recess such that optical signals emitted by the opto-electric circuitry are reflected away from the substrate and incident optical signals are reflected onto the opto-electric circuitry.

摘要翻译： 集成电路封装包括具有沿着衬底的周边的至少一部分形成的凹部的衬底和具有光电电路的光学管芯，该光学管芯耦合到衬底，使得光学管芯的一部分具有 光电电路突出了凹槽。 集成电路封装还包括设置在凹部中的光学单元，使得由光电电路发射的光信号被反射离开衬底并且入射光信号被反射到光电电路上。

公开(公告)号：US09053930B2

公开(公告)日：2015-06-09

申请号：US13736535

申请日：2013-01-08

申请人： International Business Machines Corporation

发明人： Can Bayram ,  Cheng-Wei Cheng ,  Tak H. Ning ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L29/20

CPC分类号： H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/2007 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/267

摘要： Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.

摘要翻译： 提供了将III族氮化物材料集成在硅材料上的各种方法。 在一个实施例中，该方法包括提供包括（100）硅层，位于（100）硅层的最上表面上的（111）硅层的结构，位于（100）硅层的最上表面上的第III族氮化物材料层 （111）硅层和位于III族氮化物材料层的最上表面上的绝缘材料的覆盖层。 接下来，通过电介质材料的覆盖层，III族氮化物材料层，（111）Si层并且在（100）硅层的一部分内形成开口。 然后在开口内形成电介质垫片。 然后在开口内的（100）硅层的暴露表面上形成外延半导体材料，然后进行平坦化。