公开(公告)号：US09520921B2

公开(公告)日：2016-12-13

申请号：US13905342

申请日：2013-05-30

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H04B5/00 ,  H01L23/538 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01Q1/22 ,  H01Q7/00 ,  H01F38/14 ,  A61B5/00 ,  H02J17/00

CPC classification number: H04B5/0075 ,  A61B5/6804 ,  A61B2562/164 ,  H01F38/14 ,  H01L23/5387 ,  H01L23/645 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01Q1/2225 ,  H01Q1/273 ,  H01Q1/526 ,  H01Q7/00 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/40 ,  H02J50/70 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0081 ,  H01L2924/00

Abstract: An embodiment of a network of electronic devices is formed on a flexible substrate by a plurality of electronic devices assembled on the flexible substrate. The electronic devices have an embedded antenna for mutual coupling of a wireless type. Each electronic device is formed by a chip or a complex system integrating a transceiver circuit coupled to the embedded antenna and a functional part coupled to the transceiver circuit and including at least one element chosen in the group comprising: a sensor, an actuator, an interface, an electrode, a memory, a control unit, a power-supply unit, a converter, an adapter, a digital circuit, an analog circuit, an RF circuit, a microelectromechanical system, an electrode, a well, a cell, a container for liquids. The flexible support may be a substrate of plastic material that incorporates the electronic devices or a garment having smart buttons that house the electronic devices.

Abstract translation: 通过组装在柔性基板上的多个电子装置在柔性基板上形成电子装置网络的一个实施例。 电子设备具有用于无线类型的相互耦合的嵌入式天线。 每个电子设备由芯片或复合系统形成，该系统集成耦合到嵌入式天线的收发器电路和耦合到收发器电路的功能部件，并且包括在组中选择的至少一个元件，包括：传感器，致动器，接口 ，电极，存储器，控制单元，电源单元，转换器，适配器，数字电路，模拟电路，RF电路，微机电系统，电极，阱，电池，容器 用于液体。 柔性支撑件可以是包含电子装置的塑料材料的基底或具有容纳电子装置的智能按钮的衣服。

公开(公告)号：US20160322269A1

公开(公告)日：2016-11-03

申请号：US15208269

申请日：2016-07-12

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Alessandro Finocchiaro

IPC: H01L21/66 ,  H01L23/66 ,  H01L25/065 ,  H01L23/544 ,  H01L29/06

CPC classification number: H01L28/10 ,  G01R31/2834 ,  G01R31/2889 ,  G01R31/3025 ,  H01L22/32 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L23/564 ,  H01L23/585 ,  H01L23/66 ,  H01L24/05 ,  H01L25/0657 ,  H01L29/0642 ,  H01L2223/6677 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

Abstract translation: 衬底上的集成电路包括围绕有源区并且靠近划线的位置的周边部分，其与在同一晶片上实现的其它集成电路分开。 集成电路包括至少一个导电结构，其从衬底开始在金属化的不同平面上的周边部分中延伸并形成集成天线。 在集成天线附近提供磁沟结构。

公开(公告)号：US20160320449A1

公开(公告)日：2016-11-03

申请号：US14958093

申请日：2015-12-03

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alberto Pagani

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/318536 ,  G01R31/318563

Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.

Abstract translation: 具有功能部分和测试部分的电子设备。 测试部分包括由根据寄存器序列布置在身体中的多个测试单元形成的边界扫描寄存器，其中第一测试单元被配置为形成串并转换器，并且第二测试单元被配置为形成并行 串行转换器。 测试单元各自耦合到设备的相应数据访问引脚和功能部件的相应输入/输出点，并且具有第一测试输入和测试输出。 边界扫描寄存器分别由第一测试单元和第二测试单元分别形成两个测试半路。 第一测试单元根据第一子序列直接耦合，并且第二测试单元根据第二子序列直接耦合。

公开(公告)号：US09442159B2

公开(公告)日：2016-09-13

申请号：US13716018

申请日：2012-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/317 ,  G01R31/319

CPC classification number: G01R31/2841 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31905 ,  G01R31/31926 ,  H01L22/30 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method of testing integrated circuits, including establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.

Abstract translation: 一种测试集成电路的方法，包括通过使测试设备的至少第一探针与被测集成电路的对应的物理接触端子相接触来在测试设备和被测集成电路之间建立至少第一物理通信通道; 使所述测试设备和被测集成电路交换，通过所述第一物理通信信道，从包括至少两个测试刺激和至少两个测试响应信号的组中选出的至少两个信号，其中所述至少两个信号由 由至少两个信号调制的至少一个调制载波的装置。

公开(公告)号：US09318313B2

公开(公告)日：2016-04-19

申请号：US13869124

申请日：2013-04-24

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Federico Giovanni Ziglioli

IPC: H01L29/40 ,  H01L21/00 ,  H01L21/02 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L23/544

CPC classification number: H01L21/02 ,  H01L22/14 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L24/98 ,  H01L25/0657 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02185 ,  H01L2224/022 ,  H01L2224/02215 ,  H01L2224/037 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05006 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05601 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05644 ,  H01L2224/05681 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16147 ,  H01L2224/45099 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81375 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/85375 ,  H01L2224/85805 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/05442 ,  H01L2224/81 ,  H01L2924/01073 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor structure includes at least a semiconductor body, a delimiting structure delimiting a cup-shaped recess in the body and a conductive region in the recess. The conductive region is made of a low-melting-temperature material, having a melting temperature lower than that of the materials forming the delimiting structure.

Abstract translation: 半导体结构至少包括半导体本体，限定本体中的杯形凹部的限定结构和凹部中的导电区域。 导电区域由低熔点材料制成，其熔点低于形成限定结构的材料的熔融温度。

公开(公告)号：US20160079181A1

公开(公告)日：2016-03-17

申请号：US14948569

申请日：2015-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L23/544 ,  H01L21/268 ,  H01L23/532 ,  H01L21/321 ,  H01L23/58 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

Abstract translation: 制造可追溯集成电路的方法的一个实施例包括在半导体材料功能区的晶片上形成用于实现相应的集成电路的特定功能，在相应的集成电路的每个功能区周围形成至少一个密封环，以及在每个集成电路 电路指示集成电路的信息的至少一个标记。 在每个集成电路上形成至少一个标记可以包括在可见的相应密封环的至少一部分上形成至少一个标记。

公开(公告)号：US20160049459A1

公开(公告)日：2016-02-18

申请号：US14926269

申请日：2015-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Alessandro Finocchiaro

IPC: H01L49/02 ,  H01L23/66 ,  H01L23/00 ,  H01L21/66 ,  H01L29/06 ,  H01L23/58 ,  H01L23/528

CPC classification number: H01L28/10 ,  G01R31/2834 ,  G01R31/2889 ,  G01R31/3025 ,  H01L22/32 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L23/564 ,  H01L23/585 ,  H01L23/66 ,  H01L24/05 ,  H01L25/0657 ,  H01L29/0642 ,  H01L2223/6677 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

公开(公告)号：US20150355267A1

公开(公告)日：2015-12-10

申请号：US14827796

申请日：2015-08-17

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: G01R31/27 ,  H01L23/48 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

Abstract translation: 用于进行至少一个第一通孔的电气测试的测试系统形成仅仅部分地延伸穿过第一半导体材料体的衬底的绝缘通孔结构。 测试系统具有集成在第一主体中并电耦合到绝缘通孔结构的第一电测试电路。 第一电测试电路能够检测绝缘通孔结构的至少一个电参数。

公开(公告)号：US09209385B2

公开(公告)日：2015-12-08

申请号：US14168754

申请日：2014-01-30

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L43/02 ,  G01R33/00 ,  G01R33/04

CPC classification number: H01L43/02 ,  G01R33/0005 ,  G01R33/0011 ,  G01R33/0047 ,  G01R33/04 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: An integrated magnetic sensor formed by a semiconductor chip having a surface and accommodating a magnetic via and a sensing coil. The magnetic via is formed by a cylindrical layer of ferromagnetic material that extends perpendicular to the surface of the first chip and has in cross-section an annular shape of a circular or elliptical or curvilinear type. The sensing coil surrounds the magnetic via at a distance and is connected to an electronic circuit.

Abstract translation: 由具有表面并容纳磁通孔和感测线圈的半导体芯片形成的集成磁传感器。 磁通孔由垂直于第一芯片的表面延伸的铁磁材料的圆柱形层形成，并且具有圆形或椭圆形或曲线型的环形形状。 感测线圈围绕磁通道一段距离并且连接到电子电路。

公开(公告)号：US09099453B2

公开(公告)日：2015-08-04

申请号：US13919536

申请日：2013-06-17

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli ,  Alberto Pagani

IPC: H01L23/48 ,  H01L21/50 ,  H01L23/495 ,  H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/642 ,  H01L21/441 ,  H01L21/50 ,  H01L21/561 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L28/40 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/07802 ,  H01L2924/00

Abstract: A packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor.

Abstract translation: 封装的半导体器件包括形成在侧表面上的通信焊盘，其可操作地耦合到通信电路，以便能够建立到相邻定位的封装半导体器件的无线通信信道。 可以在切割包括封装的半导体器件的块和适当定位和尺寸的导体时形成通信焊盘。