公开(公告)号：US07679925B2

公开(公告)日：2010-03-16

申请号：US11489544

申请日：2006-07-20

Applicant: Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

Inventor： Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract translation: 公开了一种具有无源元件的布线板的制造方法。 制造方法包括在第一金属箔和第二金属箔的至少一个第一表面上涂覆电阻浆料和电介质浆料中的一种或两种，每个第一表面具有第一表面和第二表面; 布置具有热塑性和热固性的绝缘板，以便面对第一金属箔的第一表面，并且将第二金属箔的第一表面侧布置成面对不同于表面的表面 绝缘板的第一金属箔面; 通过对所配置的第一金属箔，绝缘板和第二金属箔进行堆叠，加压和加热来形成双面布线板，从而将它们集成; 以及图案化第一金属箔和/或第二金属箔。

公开(公告)号：US20090273884A1

公开(公告)日：2009-11-05

申请号：US12431937

申请日：2009-04-29

Applicant: Noriyoshi Shimizu ,  Osamu Inoue

Inventor： Noriyoshi Shimizu ,  Osamu Inoue

IPC: H01G4/002 ,  B44C1/22

CPC classification number: H05K1/162 ,  H01G4/232 ,  H01G4/236 ,  H01G4/33 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/50 ,  H01L25/0652 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/09763

Abstract: There are provided an upper electrode 18 and a lower electrode which are formed like flat plates, a dielectric layer interposed between the upper electrode and the lower electrode, and a covering portion which covers an external surface of at least one of the upper electrode and the lower electrode and is formed by an insulating resin. At least one of the upper electrode and the lower electrode is provided with at least one of opening holes having larger diameters than a via formed in a connection to a wiring pattern when a capacitor component is to be included in a substrate.

Abstract translation: 设置有形成为平板的上电极18和下电极，介于上电极和下电极之间的电介质层和覆盖上电极和下电极中的至少一个的外表面的覆盖部分 并由绝缘树脂形成。 上部电极和下部电极中的至少一个设置有至少一个开口孔，当将电容器部件包括在基板中时，至少一个开口孔的直径大于与布线图案连接形成的通孔的直径。

公开(公告)号：US07607216B2

公开(公告)日：2009-10-27

申请号：US11735577

申请日：2007-04-16

Applicant: Ryuichiro Wada ,  Tetsuya Ikeda

Inventor： Ryuichiro Wada ,  Tetsuya Ikeda

IPC: H01F7/06

CPC classification number: H01F41/046 ,  H01F17/0013 ,  H05K1/0306 ,  H05K1/165 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/308 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49144

Abstract: A multilayer composite including a core made of a magnetic ceramic sintered compact disposed therein, and shrinkage restraining layers including an inorganic powder that is not substantially sintered at the sintering temperature of the green ceramic layers are sintered in order to reduce the difference in shrinkage behavior during firing between the core and the green ceramic layers.

Abstract translation: 烧结包含由设置在其中的磁性陶瓷烧结体构成的芯的多层复合体和包含在生坯陶瓷层的烧结温度下基本上不烧结的无机粉末的收缩抑制层，以减少在生陶瓷烧结体的烧结温度下的收缩行为的差异 在核心和生坯陶瓷层之间进行烧制。

公开(公告)号：US20090242256A1

公开(公告)日：2009-10-01

申请号：US12410685

申请日：2009-03-25

Applicant: Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

Inventor： Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/098

Abstract: In a dielectric element, the angle θ made by either the top face or the bottom face and the side faces is either 0°

Abstract translation: 在电介质元件中，由顶面或底面和侧面形成的角度θ为0°<89°，或91°<180°，并且为89°以外的角度 <=θ<= 91°。 通过这种方式，介电元件的侧面与玻璃环氧树脂基板和绝缘材料的接触面积增加，与树脂基板的粘附性提高，并且当埋在两个树脂之间时，可以提高强度和可靠性 底物。

公开(公告)号：US20090139760A1

公开(公告)日：2009-06-04

申请号：US12216747

申请日：2008-07-10

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H01R12/04 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including an insulation layer and a first interlayer resin insulation layer provided on the insulation layer. A layered capacitor section is provided on the first interlayer resin insulation layer and has a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. Also included is a second interlayer resin insulation layer provided on the first interlayer resin insulation layer and the layered capacitor section, and a metal thin-film layer provided over the layered capacitor section and on the second interlayer resin insulation layer. An outermost interlayer resin insulation layer is provided on the second interlayer resin insulation layer and the metal thin-film layer, and a mounting section is provided on the outermost interlayer resin insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each interlayer resin insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals, and second via conductors that electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在所述绝缘层上的绝缘层和第一层间树脂绝缘层。 层叠电容器部分设置在第一层间树脂绝缘层上，并且具有高电介质层和夹在高电介质层中的第一和第二层状电极。 还包括设置在第一层间树脂绝缘层和层状电容器部分上的第二层间树脂绝缘层和设置在层状电容器部分和第二层间树脂绝缘层上的金属薄膜层。 在第二层间树脂绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层，并且在最外层的层间树脂绝缘层上设置安装部，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个层间树脂绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体和将第二层状电极电连接到第二外部端子的第二通路导体。

公开(公告)号：US07504706B2

公开(公告)日：2009-03-17

申请号：US11514097

申请日：2006-08-31

Applicant: Madhavan Swaminathan ,  Ege Engin ,  Lixi Wan ,  Prathap Muthana

Inventor： Madhavan Swaminathan ,  Ege Engin ,  Lixi Wan ,  Prathap Muthana

IPC: H01L29/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract translation: 本发明的一个实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括在所述封装中安装嵌入式分立陶瓷电容器阵列，以及可选的平面电容层 。 另一实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括具有不同谐振频率的嵌入式分立陶瓷电容器阵列，其布置成使得电容器 阵列在关键中频范围内的阻抗与频率曲线产生等于或低于目标阻抗值的阻抗值。

公开(公告)号：US20090057910A1

公开(公告)日：2009-03-05

申请号：US11847985

申请日：2007-08-30

Applicant: Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L29/00 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US07485411B2

公开(公告)日：2009-02-03

申请号：US11700864

申请日：2007-02-01

Applicant: Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

Inventor： Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

IPC: G03C5/00

CPC classification number: H05K1/162 ,  H05K3/16 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763

Abstract: In a method for manufacturing a printed circuit board with a thin film capacitor embedded therein, a conductive metal is sputtered via a first mask to form a lower electrode. A dielectric material is sputtered via a second mask to form a dielectric layer. The conductive metal is sputtered via a third mask to form an upper electrode. An insulating layer is stacked on a stack body with the upper electrode formed therein and via holes are perforated from a top surface of the insulating layer to a top surface of the lower electrode and from the top surface of the insulating layer to a top surface of the upper electrode formed on the substrate. Also, the stack body with the via holes formed therein is electrolytically and electrolessly plated.

Abstract translation: 在其中嵌入有薄膜电容器的印刷电路板的制造方法中，通过第一掩模溅射导电金属以形成下电极。 通过第二掩模溅射介电材料以形成电介质层。 通过第三掩模溅射导电金属以形成上电极。 绝缘层堆积在堆叠体上，上电极形成在其中，并且通孔从绝缘层的顶表面穿孔到下电极的顶表面，并从绝缘层的顶表面到 上电极形成在基板上。 此外，其中形成有通孔的堆叠体是电解和无电镀的。

公开(公告)号：US20090023858A1

公开(公告)日：2009-01-22

申请号：US12141137

申请日：2008-06-18

Applicant: JOHN D. SUMMERS ,  THOMAS EUGENE DUEBER

Inventor： JOHN D. SUMMERS ,  THOMAS EUGENE DUEBER

IPC: C08L77/10 ,  C08G69/32 ,  B41M1/12

CPC classification number: H05K1/162 ,  C08G69/00 ,  C08G73/22 ,  H01L51/5253 ,  H05K3/1291 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

Abstract translation: 本发明涉及组合物，以及这些组合物用于保护涂层，特别是电子器件的用途。 本发明涉及涂覆有复合密封剂并嵌入印刷线路板的烧制箔陶瓷电容器。

公开(公告)号：US20080297274A1

公开(公告)日：2008-12-04

申请号：US12188271

申请日：2008-08-08

Applicant: WILLIAM J. BORLAND ,  G. Sidney Cox ,  David Ross McGregor

Inventor： WILLIAM J. BORLAND ,  G. Sidney Cox ,  David Ross McGregor

IPC: H03H7/00 ,  H01G4/00

CPC classification number: H05K1/167 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K2203/1461 ,  Y10T29/435

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.

Abstract translation: 本发明涉及可以嵌入在印刷线路板的层内的电容/电阻装置。 嵌入器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。 更具体地，该装置包括第一金属箔; 第二金属箔; 由所述第一金属箔形成的第一电极; 设置在所述第一电极上的电介质; 形成在电介质上并与电介质相邻的电阻元件; 导电迹线 以及由所述第二金属箔形成并且设置在所述电介质上并与所述电阻元件电接触的第二电极，其中所述电介质设置在所述第一电极和所述第二电极之间，并且其中所述电介质包括介电常数小于 4.0。