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    Via including multiple electrical paths
    4.
    发明授权
    Via including multiple electrical paths 有权
    通过包括多个电路径

    公开(公告)号：US07183653B2

    公开(公告)日：2007-02-27

    申请号：US10740957

    申请日：2003-12-17

    申请人： Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Renee M Defeo ,  Jui Min Lim

    发明人： Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Renee M Defeo ,  Jui Min Lim

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/064 ,  H05K3/403 ,  H05K3/4644 ,  H05K2201/09645 ,  H05K2201/09827 ,  H01L2924/00

    摘要： A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

    摘要翻译： 一种系统包括具有至少一个集成电路的装置。 集成电路还包括第一导电材料层，第二导电材料层，以及具有用于互连导电材料的第一层和第二导电材料层的多条电路的通路。 用于形成通孔的方法包括将开口钻出一定深度以露出第一垫和第二垫，用导电材料衬套开口，并将开口中的衬里的第一部分与衬里的第二部分绝缘 所述开口形成接触所述第一焊盘的第一电路径和与所述第二焊盘接触的第二电路径。

    METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE
    10.
    发明申请
    METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE 有权
    强化无缝封装基板的方法

    公开(公告)号：US20100301492A1

    公开(公告)日：2010-12-02

    申请号：US12857332

    申请日：2010-08-16

    申请人： Sriram Muthukumar ,  Nicholas R. Watts ,  John S. Guzek

    发明人： Sriram Muthukumar ,  Nicholas R. Watts ,  John S. Guzek

    IPC分类号： H01L23/522

    CPC分类号： H01L23/49822 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0271 ,  H05K3/28 ,  H05K3/4682 ,  H05K2203/0582 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

    摘要翻译： 本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。 该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度 并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。 实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。