公开(公告)号：US06538463B2

公开(公告)日：2003-03-25

申请号：US10078982

申请日：2002-02-20

申请人： Walter L. Moden ,  John O. Jacobson

发明人： Walter L. Moden ,  John O. Jacobson

IPC分类号： G01R3128

CPC分类号： G01R1/04 ,  G01R1/0483 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2924/01019 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention uses a die cut piece of adhesively coated tape to hold a die in a test and burn-in fixture. Upon subsequent heating of the tape beyond the normal operating range of the adhesive coating on the tape, the die is removed from the tape, the tape is removed from the test and burn-in fixture, and the remaining adhesive, if any, is removed from the test and burn-in fixture.

摘要翻译： 在测试和老化期间使用胶带临时保持模具临时保持在固定装置中的方法。 本发明的方法使用粘合涂覆带的模切片将模具保持在测试和老化固定装置中。 在随后将带加热超过胶带上的粘合剂涂层的正常操作范围之后，将模具从带上移除，将带从测试和老化固定装置中取出，并且剩余的粘合剂（如果有的话）被去除 从测试和老化装置。

公开(公告)号：US06492728B2

公开(公告)日：2002-12-10

申请号：US09837310

申请日：2001-04-18

申请人： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

发明人： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

IPC分类号： H01L2332

CPC分类号： H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

摘要翻译： 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 优选地，半导体器件的至少一部分被暴露。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。

公开(公告)号：US06475831B2

公开(公告)日：2002-11-05

申请号：US09792771

申请日：2001-02-23

申请人： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

发明人： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

IPC分类号： H01L2148

CPC分类号： H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/00

摘要： A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

摘要翻译： 用于高速应用的低调多IC芯片封装包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。 在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一端形成有总线。 在另一个实施例中，连接器包括由导电聚合物形成的多个总线。 在另外的实施例中，初级封装堆叠在保持架内并且使它们的外部引线与保持架内的总线不连接地接触，或者替代地直接固定到主电路板上的引线或焊盘上。

公开(公告)号：US06419517B1

公开(公告)日：2002-07-16

申请号：US09261608

申请日：1999-02-26

申请人： Walter L. Moden

发明人： Walter L. Moden

IPC分类号： H01R1364

CPC分类号： H01R12/7005 ,  H01R12/714

摘要： The invention relates to a circuit package comprising a module and a socket which cooperate to provide quick and easy insertion of the module into the socket using a small insertion force, accurate alignment between the module and the socket after insertion, and coupling between a module coupling site and a socket coupling site after insertion. A socket guide feature allows an edge of the module to slide along the guide feature during insertion of the module into the socket, and a module alignment feature interlocks with a socket alignment feature-after insertion of the module into the socket. In addition, after insertion of the module into the socket, a retaining feature restricts the motion of the module so that the module coupling site remains in contact with the socket coupling site.

摘要翻译： 本发明涉及一种电路封装，其包括模块和插座，其协作以使用小的插入力将模块快速和容易地插入插座中，插入之后模块和插座之间的精确对准以及模块耦合 插入后的现场和插座耦合部位。 插座引导功能允许模块的边缘在将模块插入插座期间沿引导功能滑动，并且模块对准功能与插座对准功能互锁 - 将模块插入插座后。 此外，在将模块插入插座之后，保持特征限制模块的运动，使得模块耦合部位保持与插座耦合部位接触。

公开(公告)号：US06384333B1

公开(公告)日：2002-05-07

申请号：US09923929

申请日：2001-08-07

申请人： Walter L. Moden

发明人： Walter L. Moden

IPC分类号： H01L2302

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00012

摘要： A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

摘要翻译： 公开了一种LOC模头组件，其包括介电粘附到引线框架的下侧的模具。 在每个引线指和半导体管芯之间引入底部填充材料，其从模具的结合位置和模具的边缘延伸，以防止填料颗粒在传递模塑期间在引线和模具的有效表面之间倒伏 塑料密封剂。 由底部填充材料产生的密封通常由填料颗粒引起的在模具的活性表面上降低点应力。 引线中的弯曲减小进一步增强了引线相对于管芯的位置锁定。

公开(公告)号：US06329709B1

公开(公告)日：2001-12-11

申请号：US09076334

申请日：1998-05-11

申请人： Walter L. Moden ,  Larry D. Kinsman ,  Warren M. Farnworth

发明人： Walter L. Moden ,  Larry D. Kinsman ,  Warren M. Farnworth

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00013 ,  H01L2924/013

摘要： A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

摘要翻译： 一种用于形成用于半导体器件的电接触的方法包括以下步骤：提供具有主表面的半导体晶片部分，其上具有多个导电焊盘，并使每个焊盘与细长的电互连电连接。 接下来，每个电互连被封装在电介质中，并且电介质被分段以暴露每个互连的一部分。 还描述了可以通过本发明方法形成的本发明的结构。

公开(公告)号：US06326242B1

公开(公告)日：2001-12-04

申请号：US09430559

申请日：1999-10-29

申请人： Mike Brooks ,  Walter L. Moden

发明人： Mike Brooks ,  Walter L. Moden

IPC分类号： H01L2144

CPC分类号： H01L23/36 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H05K3/341 ,  H05K2201/10689 ,  H05K2201/1078 ,  H05K2201/1084 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00

摘要： A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

摘要翻译： 提供一种用于制造封装的半导体封装和方法。 封装包括半导体管芯和与管芯热连通的散热器。 散热器包括适于形成接合连接的一个或多个焊盘结构，以及衬底上的触点的热路径。 该方法包括在类似于引线框架的框架上形成多个散热器，以及蚀刻或冲压散热器上的焊盘结构。 然后可以将该框架连接到包含封装的骰子的引线框架上，并且该组件被单个化以形成单独的封装。 这些封装可用于形成诸如电路板组件和多芯片模块之类的电子组件。

公开(公告)号：US06310288B1

公开(公告)日：2001-10-30

申请号：US09606976

申请日：2000-06-28

申请人： Walter L. Moden

发明人： Walter L. Moden

IPC分类号： H01L2302

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10T29/49121 ,  Y10T428/24165 ,  Y10T428/24207 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

摘要翻译： 公开了一种LOC模具组件，其包括介电粘附到引线框架的下侧的模具。 在每个引线指和半导体管芯之间引入底部填充材料，其从模具的结合位置和模具的边缘延伸，以防止填料颗粒在传递模塑期间在引线和模具的有效表面之间倒伏 塑料密封剂。 由底部填充材料产生的密封通常由填料颗粒引起的在模具的活性表面上降低点应力。 引线中的弯曲减小进一步增强了引线相对于管芯的位置锁定。

公开(公告)号：US06297960B1

公开(公告)日：2001-10-02

申请号：US09344284

申请日：1999-06-30

申请人： Walter L. Moden ,  David J. Corisis ,  Larry D. Kinsman ,  Leonard E. Mess

发明人： Walter L. Moden ,  David J. Corisis ,  Larry D. Kinsman ,  Leonard E. Mess

IPC分类号： H05K720

CPC分类号： H01L23/3675 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/0002 ,  Y10T428/24298 ,  H01L2924/00

摘要： An apparatus for providing heat sinks or heat spreaders for stacked semiconductor devices. Alignment apparatus may be included for the alignment of the stacked semiconductor devices. An enclosure may be used as the heat sink or heat spreader.

摘要翻译： 一种用于为叠层半导体器件提供散热器或散热器的设备。 可以包括对准装置用于堆叠的半导体器件的对准。 可以使用外壳作为散热器或散热器。

公开(公告)号：US06268649B1

公开(公告)日：2001-07-31

申请号：US09537879

申请日：2000-03-29

申请人： David J. Corisis ,  Jerry M. Brooks ,  Walter L. Moden

发明人： David J. Corisis ,  Jerry M. Brooks ,  Walter L. Moden

IPC分类号： H01L2302

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements. Additionally, certain pins on the FBGA in the stack require an isolated connection to the PC board. Yet, this isolated connection should be able to be connected to an adjacent ball on a different FBGA stack above or below that particular isolated connection. This provides for a stair step connection from the bottom of the FBGA stacked array to the top. This allows IC devices to be stacked one upon the other while maintaining a unique pin out for each pin required in the stack.