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公开(公告)号:US10268412B2
公开(公告)日:2019-04-23
申请号:US15720920
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: James D. Guilford , Vinodh Gopal , Daniel F. Cutter
IPC: H03M7/30 , G06F3/06 , G06F17/30 , H03M7/40 , H04L12/26 , H04L12/813 , H04L12/851 , G06F11/07 , G06F11/30 , G06F11/34 , G06F7/06 , G06T9/00 , H03M7/42 , H04L12/28 , H04L12/46 , H04L29/12 , G06F13/16 , G06F21/62 , G06F21/76 , H03K19/173 , H04L9/08 , H04L12/24 , H04L12/933 , H04L29/08 , G06F9/38 , G06F9/48 , G06F9/50 , G06F12/02 , G06F12/06 , G06T1/20 , G06T1/60 , G06F9/54 , G06F8/656 , G06F8/658 , G06F8/654 , G06F9/4401 , H01R13/453 , H01R13/631 , H05K7/14 , G06F21/57 , G06F21/73 , G06F8/65 , G06F11/14 , H04L29/06 , G06F15/80
Abstract: A compute device to generate deterministic compressed streams receives a current string to be matched to one or more prior instances of the current string, the current string being located within an input buffer and the one or more prior instances located within a history buffer. The compute device identifies a limited subset of index memory designated for storing pointers to the prior instances, identifying a reserved slop region in the index memory, and compares the current string to a prior instance, locating the at least one prior instance using at least one pointer to the at least one prior instance. The at least one pointer is stored within the limited subset of the index memory, and the compute device also prohibits use of any pointers stored in the reserved slop region of the index memory. Other embodiments are described and claimed.
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公开(公告)号:US10224956B2
公开(公告)日:2019-03-05
申请号:US15816959
申请日:2017-11-17
Applicant: Intel Corporation
Inventor: Vinodh Gopal , James D. Guilford , Daniel F. Cutter
Abstract: In one embodiment, an apparatus comprises a first compression engine to receive a first compressed data block from a second compression engine that is to generate the first compressed data block by compressing a first plurality of repeated instances of data that each have a length greater than or equal to a first length. The first compression engine is further to compress a second plurality of repeated instances of data of the first compressed data block that each have a length greater than or equal to a second length, the second length being shorter than the first length, wherein each compressed repeated instance of the first and second pluralities of repeated instances comprises a location and length of a data instance that is repeated. The apparatus further comprises a memory buffer to store the compressed first and second plurality of repeated instances of data.
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公开(公告)号:US10218739B2
公开(公告)日:2019-02-26
申请号:US15049519
申请日:2016-02-22
Applicant: Intel Corporation
Inventor: Vinodh Gopal , Christopher F. Clark , Gilbert M. Wolrich , Wajdi K. Feghali
Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
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公开(公告)号:US20180375527A1
公开(公告)日:2018-12-27
申请号:US15875836
申请日:2018-01-19
Applicant: Intel Corporation
Inventor: Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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公开(公告)号:US10164769B2
公开(公告)日:2018-12-25
申请号:US14984588
申请日:2015-12-30
Applicant: Intel Corporation
Inventor: Shay Gueron , Wajdi K Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G Dixon , Srinivas Chennupaty , Michael E Kounavis
IPC: H04L9/28 , G06F21/72 , H04L9/06 , H04L9/08 , G06F12/14 , G06F21/60 , G06F12/0875 , G06F9/30 , G06F12/0862 , G06F9/38 , G11C7/10 , G06F3/06
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号:US10069512B2
公开(公告)日:2018-09-04
申请号:US15479087
申请日:2017-04-04
Applicant: Intel Corporation
Inventor: Vinodh Gopal , James D. Guilford , Kirk S. Yap , Sean M. Gulley , Gilbert M. Wolrich
Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.
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167.
公开(公告)号:US20180234258A1
公开(公告)日:2018-08-16
申请号:US15434194
申请日:2017-02-16
Applicant: Intel Corporation
Inventor: Simon N. Peffers , Sean M. Gulley , Vinodh Gopal , Sanu K. Mathew
CPC classification number: H04L63/0428 , G06F1/04 , G06F16/00 , G09C1/00 , H04L9/0866 , H04L63/0876
Abstract: In one embodiment, an apparatus includes: a device having a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal; a controller coupled to the device, the controller to send the at least one control signal to the PUF circuit and to receive a plurality of PUF samples from the PUF circuit; a buffer having a plurality of entries each to store at least one of the plurality of PUF samples; and a filter to filter the plurality of PUF samples to output a filtered value, wherein the controller is to generate a unique identifier for the device based at least in part on the filtered value. Other embodiments are described and claimed.
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公开(公告)号:US10033404B2
公开(公告)日:2018-07-24
申请号:US15639289
申请日:2017-06-30
Applicant: Intel Corporation
Inventor: Daniel F. Cutter , Vinodh Gopal , James D. Guilford
Abstract: Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at a present position and a predefined number of symbols after the present position in an input stream, determine whether the symbol at the present position is part of a run, obtain, from a hash table, a chain of pointers to previous positions in the input stream associated with the hash, determine, as a function of whether the symbol is part of a run and to identify a matched string, a number of strings referenced by the chain of pointers to compare to a string associated with the present position in the input stream, and output, in response to an identification of a matched string, a reference to the matched string in a set of compressed output data.
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公开(公告)号:US20180205392A1
公开(公告)日:2018-07-19
申请号:US15854261
申请日:2017-12-26
Applicant: Intel Corporation
Inventor: Vinodh Gopal , James D. Guilford , Kirk S. Yap
IPC: H03M7/40
CPC classification number: H03M7/3084 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F17/30949 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0005 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/14 , Y02D10/151 , Y02P90/30 , Y10S901/01
Abstract: Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a deterministic decoder and concurrently perform speculative decodes over a range of subsequent positions in the compressed data, determine the position of the next code, determine whether the position of the next code is within the range, and output, in response to a determination that the position of the next code is within the range, a symbol associated with the deterministically decoded code and another symbol associated with a speculatively decoded code at the position of the next code.
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公开(公告)号:US10009172B2
公开(公告)日:2018-06-26
申请号:US15401877
申请日:2017-01-09
Applicant: INTEL CORPORATION
Inventor: Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
CPC classification number: H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
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