中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

351 records (took 0.049 seconds)

    Power core devices and methods of making thereof
    161.
    发明申请
    Power core devices and methods of making thereof 有权
    电力核心装置及其制造方法

    公开(公告)号：US20070090511A1

    公开(公告)日：2007-04-26

    申请号：US11514094

    申请日：2006-08-31

    Applicant: William Borland ,  Saul Ferguson

    Inventor： William Borland ,  Saul Ferguson

    IPC: H01L23/52 ,  H01L21/00

    CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K2201/10734

    Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.

    Abstract translation: 一种包括功率核心的器件，其中所述功率核心包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入的单个电容器，其中所述嵌入式单电容器包括至少第一电极和第二电极，并且其中所述嵌入式单个电容器位于 功率核心的外层，电源芯的外层上的电容器的第一和第二电极都具有电源核心的外层，使得半导体器件的至少一个Vcc（功率）端子和至少一个Vss（接地）端子可以直接 分别连接到至少一个第一和至少一个第二电极。

    Reactively formed integrated capacitors on organic substrates and fabrication methods
    162.
    发明申请
    Reactively formed integrated capacitors on organic substrates and fabrication methods 审中-公开
    在有机基板上反应形成集成电容器和制造方法

    公开(公告)号：US20060269762A1

    公开(公告)日：2006-11-30

    申请号：US11363334

    申请日：2006-02-27

    Applicant: Markondeya Pulugurtha ,  Devarajan Balaraman ,  Rao Tummala ,  Isaac Abothu

    Inventor： Markondeya Pulugurtha ,  Devarajan Balaraman ,  Rao Tummala ,  Isaac Abothu

    IPC: B32B15/04

    CPC classification number: H05K1/162 ,  H01G4/10 ,  H01G4/33 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/121 ,  Y10T428/31678

    Abstract: Disclosed are organic-compatible thin film processing techniques with reactive (such as Ti) layers for embedding capacitors into substrates. Hydrothermal synthesis allows direct deposition of high-k films with capacitance density of about 1 μF/cm2 on organic substrates. This is done by reactively growing a high-k film from Ti foil/Ti-coated copper foil/Ti precursor-coated organic substrate in an alkaline barium ion bath. Alternatives may be used to address multiple coatings, low temperature baking, low temperature pyrolysis with oxygen plasma, etc. Sol-gel and RF-sputtering assisted by a reaction with the intermediate layer and a foil transfer process may be used to integrate perovskite thin films with a capacitance in the range of 1-5 μF/cm2. Thermal oxidation of titanium foil/Ti-coated copper foil/Ti-coated organic substrate with a copper conductive layer is also a reactively grown high-k film process for integrating capacitance of hundreds of nF with or without using a foil transfer process.

    Abstract translation: 公开了具有用于将电容器嵌入衬底中的反应性（例如Ti）层的有机相容薄膜处理技术。 水热合成允许在有机衬底上直接沉积具有约1μF/ cm 2的电容密度的高k膜。 这是通过在碱性钡离子浴中从Ti箔/ Ti涂覆的铜箔/ Ti前体涂覆的有机衬底上反应生长高k膜而完成的。 替代品可用于处理多层涂料，低温烘烤，氧等离子体的低温热解等。通过与中间层反应和箔转移工艺进行辅助的溶胶 - 凝胶和RF溅射可用于整合钙钛矿薄膜 电容量在1-5μF/ cm 2之间。 具有铜导电层的钛箔/ Ti涂覆的铜箔/ Ti涂覆的有机衬底的热氧化也是用于利用或不使用箔转移工艺来集成数百nF的电容的反应生长的高k膜工艺。

    Oxygen doped firing of barium titanate on copper foil
    164.
    发明申请
    Oxygen doped firing of barium titanate on copper foil 审中-公开
    钛酸钡在铜箔上的氧掺杂烧制

    公开(公告)号：US20060141225A1

    公开(公告)日：2006-06-29

    申请号：US11023815

    申请日：2004-12-28

    Applicant: William Borland

    Inventor： William Borland

    IPC: B05D5/12 ,  B32B3/00

    CPC classification number: H01G4/1227 ,  H05K1/092 ,  H05K1/162 ,  H05K3/1291 ,  H05K2201/017 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126 ,  Y10T428/24917

    Abstract: The present invention relates to a method of making an embedded capacitor and a printed wiring board includes providing a metallic foil; forming a first dielectric layer over the metallic foil; forming a conductive layer over at least a portion of the first dielectric layer; controlling an oxygen content of a controlled atmosphere; and firing the first dielectric layer and the conductive layer in a firing zone in the controlled atmosphere.

    Abstract translation: 本发明涉及一种制造嵌入式电容器和印刷电路板的方法，包括提供金属箔; 在所述金属箔上形成第一电介质层; 在所述第一介电层的至少一部分上形成导电层; 控制受控气氛的氧含量; 以及在受控气氛中的烧制区中焙烧第一介电层和导电层。

    Method of producing ceramic multilayer substrate
    168.
    发明授权
    Method of producing ceramic multilayer substrate 有权
    陶瓷多层基板的制造方法

    公开(公告)号：US07004984B2

    公开(公告)日：2006-02-28

    申请号：US10753535

    申请日：2004-01-09

    Applicant: Junzo Fukuta ,  Satoru Adachi

    Inventor： Junzo Fukuta ,  Satoru Adachi

    IPC: H01M6/00 ,  B32B31/14

    CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/167 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/09763 ,  H05K2203/061 ,  H05K2203/171 ,  Y10T29/49112 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49162 ,  Y10T29/49163 ,  H01L2924/00

    Abstract: After a resistor and/or a capacitor are simultaneously fired on a fired ceramic core substrate to be fired, the fired resistor and/or the fired capacitor is trimmed so that the resistance and the capacitance are adjusted. Thereafter, an after-lamination green sheet is laminated onto the ceramic core substrate and the produced after-lamination substrate is fired at a temperature which is lower than the sintering temperature of the resistor and the dielectric. Thus, the sintered resistor and dielectric can be prevented from being softened and melted when the after-lamination substrate is fired. Moreover, the resistance and the capacitance accurately adjusted by trimming before the after-lamination substrate is fired are not changed by the firing.

    Abstract translation: 在烧结的烧结陶瓷芯基板上同时点燃电阻器和/或电容器之后，对烧结的电阻器和/或烧结电容器进行微调，以便调节电阻和电容。 然后，在陶瓷芯基板上层压分层后的生片，在低于电阻体和电介质的烧结温度的温度下烧制所制造的叠层后基板。 因此，烧结的电阻体和电介质可以防止在后层压衬底被烧制时软化和熔化。 此外，烧结之前通过在叠层后基板被修整而精确调节的电阻和电容不会因烧制而改变。

    Integrated thin film capacitor/inductor/interconnect system and method
    169.
    发明授权
    Integrated thin film capacitor/inductor/interconnect system and method 失效
    集成薄膜电容/电感/互连系统及方法

    公开(公告)号：US06998696B2

    公开(公告)日：2006-02-14

    申请号：US10686116

    申请日：2003-10-15

    Applicant: Michael D. Casper ,  William B. Mraz

    Inventor： Michael D. Casper ,  William B. Mraz

    IPC: H01L29/00

    CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

    Abstract translation: 公开了用于在各种薄膜混合基板表面（0501）上制造高可靠性电容器（1011），电感器（1012）和多层互连（1013）（包括电阻器（1014））的系统和方法。 所公开的方法首先采用在衬底（0501）上沉积和图案化的薄金属层（0502）。 该薄图案层（0502）用于为上电极组件之间的电容器结构（0603）和互连（0604）提供两个下电极。 接下来，在薄的图案化层（0502）上沉积电介质层（0705），并且对电介质层（0705）进行图案化以将薄的图案化层的接触孔（0806）打开。 然后将上电极层（0907,0908,1009,1010）沉积并图案化在电介质（0705）的顶部。

Patent Agency Ranking