公开(公告)号：US08502375B2

公开(公告)日：2013-08-06

申请号：US12825617

申请日：2010-06-29

Applicant: Chih-Chin Liao ,  Cheeman Yu

Inventor： Chih-Chin Liao ,  Cheeman Yu

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/50 ,  H01L24/04 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01013 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die.

Abstract translation: 公开了一种由其形成的半导体管芯和半导体封装以及半导体管芯和封装件的制造方法。 半导体管芯包括形成有由凹陷之间的突起限定的多个波纹的边缘。 接合焊盘可以形成在突起上。 以这种方式形成的半导体管芯可以以交错对堆叠在半导体封装中，使得下模具的突起上的管芯接合焊盘位于上模的凹部中。

公开(公告)号：US20130015589A1

公开(公告)日：2013-01-17

申请号：US13265662

申请日：2011-07-14

Applicant: Chih-Chin Liao ,  Chin-Tien Chiu ,  Cheeman Yu ,  Suresh Kumar Upadhyayula ,  Wen Cheng Li ,  Zhong Lu

Inventor： Chih-Chin Liao ,  Chin-Tien Chiu ,  Cheeman Yu ,  Suresh Kumar Upadhyayula ,  Wen Cheng Li ,  Zhong Lu

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multi-die semiconductor device is disclosed. The device may include one or more first-sized die on a substrate and one or more second-sized die affixed over the one or more first-sized die. The second-sized die may have a larger footprint than the first-sized die. An internal molding compound may be provided on the substrate having a footprint the same size as the second-sized die. The second-sized die may be supported on the internal molding compound. Thereafter, the first and second-sized die and the internal molding compound may be encapsulated in an external molding compound.

Abstract translation: 公开了一种多芯片半导体器件。 该装置可以包括在基底上的一个或多个第一尺寸的模具和一个或多个第二尺寸的模具，该模具固定在一个或多个第一尺寸模具上。 第二尺寸的模具可以具有比第一尺寸的模具更大的占地面积。 可以在衬底上设置内部模制化合物，其尺寸与第二尺寸模具相同。 第二尺寸的模具可以支撑在内部模塑料上。 此后，第一和第二尺寸模具和内部模塑料可以封装在外部模塑料中。

公开(公告)号：US08232145B2

公开(公告)日：2012-07-31

申请号：US12614960

申请日：2009-11-09

Applicant: Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

Inventor： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

IPC: H01L21/00

CPC classification number: G06K19/077 ,  B29C45/14311 ,  B29C45/14647 ,  B29C2045/14327 ,  G06K19/07724 ,  G06K19/07732 ,  H01L23/10 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract translation: 公开了一种闪存卡及其制造方法。 卡包括制造成接收单面或双面盖的半导体封装。 半导体封装的表面可以形成有孔，沟槽和/或戳记。 在形成孔，沟和/或标记之后，可以在注射成型工艺中将盖子附接到包装表面。 在注射成型过程中，熔融的塑料流入与半导体封装的表面互连的孔，沟槽和/或戳痕。 因此，当熔融塑料硬化时，孔，沟槽和/或戳痕确保盖保持牢固地附接到半导体封装。

公开(公告)号：US08053276B2

公开(公告)日：2011-11-08

申请号：US12614981

申请日：2009-11-09

Applicant: Cheeman Yu ,  Chi-Chin Liao ,  Hem Takiar

Inventor： Cheeman Yu ,  Chi-Chin Liao ,  Hem Takiar

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L24/49 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract translation: 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US09209159B2

公开(公告)日：2015-12-08

申请号：US13411308

申请日：2012-03-02

Applicant: Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

公开(公告)号：US20140015116A1

公开(公告)日：2014-01-16

申请号：US14008457

申请日：2011-12-16

Applicant: Peng Fu ,  Shan Luo ,  Zhong Lu ,  Kaiyou Qian ,  Chin Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Ye Bai

Inventor： Peng Fu ,  Shan Luo ,  Zhong Lu ,  Kaiyou Qian ,  Chin Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Ye Bai

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed. The metallic layer is formed on a metallic layer transfer assembly. The metallic layer transfer assembly and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the metallic layer is transferred from the shield to the encapsulated memory device.

Abstract translation: 公开了一种包括屏蔽电磁辐射和/或耗散热的金属层的存储器件，以及制造存储器件的方法。 金属层形成在金属层转移组件上。 将金属层转移组件和未封装的存储器件放置在模具中并封装。 在模塑料的包封和固化期间，金属层从屏蔽转移到封装的存储器件。

公开(公告)号：US08482139B2

公开(公告)日：2013-07-09

申请号：US12614945

申请日：2009-11-09

Applicant: Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

Inventor： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

IPC: H01L23/29

CPC classification number: G06K19/077 ,  B29C45/14311 ,  B29C45/14647 ,  B29C2045/14327 ,  G06K19/07724 ,  G06K19/07732 ,  H01L23/10 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

公开(公告)号：US08415808B2

公开(公告)日：2013-04-09

申请号：US12844959

申请日：2010-07-28

Applicant: Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

Inventor： Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

IPC: H01L23/48

CPC classification number: H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.

Abstract translation: 公开了一种半导体管芯封装。 半导体封装的示例包括散布有第二组半导体管芯的第一组半导体管芯。 来自第一组和第二组的模具沿着第一轴线彼此偏移并且沿着与第一轴线正交的第二轴线相对于彼此交错。 半导体封装的第二示例包括不规则形状的边缘和从封装中的最低半导体管芯上方的半导体管芯到基板的引线接合。

公开(公告)号：US08349655B2

公开(公告)日：2013-01-08

申请号：US12819818

申请日：2010-06-21

Applicant: Cheeman Yu ,  Vani Verma ,  Hem Takiar

Inventor： Cheeman Yu ,  Vani Verma ,  Hem Takiar

IPC: H01L21/44

CPC classification number: H01L23/4951 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.

Abstract translation: 公开了一种制造基于引线框的半导体封装的方法以及由此形成的半导体封装。 在实施例中，具有沿两个相邻边缘的管芯接合焊盘的半导体管芯可以电耦合到四面引线框架的四个侧面。 实施例涉及引线和无引线型引线框架。

公开(公告)号：US08217522B2

公开(公告)日：2012-07-10

申请号：US12819840

申请日：2010-06-21

Applicant: Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheeman Yu ,  Hem Takiar

Inventor： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheeman Yu ,  Hem Takiar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract translation: 公开了具有共同的电连接器和接触焊盘区域的印刷电路板。 迹线和/或通孔所在接触焊盘区域可被蚀刻掉，以确保迹线，通孔和接触焊盘之间的电气隔离。