公开(公告)号：US20060038278A1

公开(公告)日：2006-02-23

申请号：US11199273

申请日：2005-08-09

Applicant: Chung-Cheng Wang

Inventor： Chung-Cheng Wang

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A submember for electrical device is disclosed. Said submember is mounted on a chip of electrical device. An embodiment for the submember comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator and a portion of conductive element exposed to the insulator for electrical connection, then (i). the reliability of submember is enhanced; (ii).the material of insulator enables to be saved; and (iii).the thickness of submember is thinner and the heat dissipation of chip enhanced; moreover, a portion of the conductive element may be protruding the insulator for avoiding a short-circuited problem of conductive wire, moreover, the conductive element may be staircase-shaped, then, not only the reliability of submember is enhanced, but the short circuit problem of conductive wire is also avoided; the conductive element may further include an extending portion, furthermore, the conductive element may be placed in a cavity as required.

Abstract translation: 公开了一种用于电气设备的子部件。 所述子部件安装在电气设备的芯片上。 一种由绝缘体和多个导电元件组成的子元件的实施例，其中嵌入绝缘体中的导电元件和暴露于绝缘体的导电元件的一部分用于电连接，然后（i）。 次级成员的可靠性得到提升; （ii）绝缘材料能够节省; 和（iii），子部件的厚度较薄，芯片的散热增强; 此外，导电元件的一部分可以突出绝缘体，以避免导线的短路问题，此外，导电元件可以是阶梯形的，因此不仅可以提高子元件的可靠性，而且短路 也避免了导线问题; 导电元件还可以包括延伸部分，此外，导电元件可以根据需要放置在空腔中。

公开(公告)号：US20050137816A1

公开(公告)日：2005-06-23

申请号：US10707519

申请日：2003-12-19

Applicant: Chao-Shi Chuang ,  Chung-Cheng Wang ,  Wen-Shih Lu

Inventor： Chao-Shi Chuang ,  Chung-Cheng Wang ,  Wen-Shih Lu

IPC: G06F19/00 ,  H03L7/08 ,  H03L7/089 ,  H03L7/099 ,  H03L7/113 ,  H03L7/18 ,  H03L7/199

CPC classification number: H03L7/113 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/199

Abstract: A PLL includes a loop filter for accumulating charge to generate a loop-filter voltage and a VCO having a plurality of frequency ranges. The VCO receives the loop-filter voltage and generates an output signal having a frequency according to the loop-filter voltage and a currently selected VCO frequency range. During PLL calibration, the loop-filter is connected to a constant voltage source; the PLL feedback signal is synchronized with the reference signal; a linear search, a binary search, or a memory lookup is used to find a first and a second VCO frequency range; first and second time durations are measured for the time durations between the second rising edges of the reference signal and the PLL feedback signal for the two VCO frequency ranges, and the optimal VCO frequency range is determined by setting the VCO frequency range to be the VCO frequency range having the shortest measured time duration.

Abstract translation: PLL包括用于累积电荷以产生环路滤波器电压的环路滤波器和具有多个频率范围的VCO。 VCO接收环路滤波器电压，并产生具有根据环路滤波器电压和当前选择的VCO频率范围的频率的输出信号。 在PLL校准期间，环路滤波器连接到恒定电压源; PLL反馈信号与参考信号同步; 使用线性搜索，二进制搜索或存储器查找来找到第一和第二VCO频率范围; 对于参考信号的第二上升沿和两个VCO频率范围的PLL反馈信号之间的持续时间测量第一和第二持续时间，并且通过将VCO频率范围设置为VCO来确定最佳VCO频率范围 频率范围具有最短的测量持续时间。

公开(公告)号：US20050104205A1

公开(公告)日：2005-05-19

申请号：US10944808

申请日：2004-09-21

Applicant: Chung-Cheng Wang

Inventor： Chung-Cheng Wang

IPC: H01L21/68 ,  H01L23/24 ,  H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H01L25/10 ,  H05K1/18 ,  H05K3/06 ,  H05K3/40 ,  H01L23/04

CPC classification number: H01L21/6835 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/064 ,  H05K3/403 ,  H05K2201/09036 ,  H05K2201/09645 ,  H05K2201/09845 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the insulator having a recess. The conductive elements embedded in the insulator. The conductive elements extend from the insulator surface to the recess. There are two portions of the conductive elements for electrical connection respectively, wherein a portion of conductive element may protrude the insulator surface for electrical connection. In this manner, solder balls are not needed. Moreover, the substrate of the present invention may also comprise an adhesive mean, which is between the conductive elements and the insulator. In addition, the substrate may further comprise a submember such as a chip, heat spreader etc., and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production.

Abstract translation: 公开了用于电气装置的基板和制造这种基板的方法。 用于由绝缘体和多个导电元件组成的衬底的实施例，其中绝缘体具有凹部。 绝缘子中嵌入的导电元件。 导电元件从绝缘体表面延伸到凹槽。 用于电连接的导电元件分为两部分，其中导电元件的一部分可以突出绝缘体表面用于电连接。 以这种方式，不需要焊球。 此外，本发明的基底还可以包括位于导电元件和绝缘体之间的粘合剂。 此外，基板还可以包括诸如芯片，散热器等的子部件，并且本发明可以提供更薄的电气设备厚度，增强的可靠性和降低的生产成本。

公开(公告)号：US20220387756A1

公开(公告)日：2022-12-08

申请号：US17830845

申请日：2022-06-02

Applicant: Chung-Cheng Wang ,  Yung-Ping Wang ,  Yi-Yuan Chen ,  Chia-Ming Hsu ,  Ming-Chien Chiu ,  Chia-Ch Lin

Inventor： Chung-Cheng Wang ,  Yung-Ping Wang ,  Yi-Yuan Chen ,  Chia-Ming Hsu

IPC: A61M25/01

Abstract: A urinary catheter conveying device includes a sleeve member, a conveying assembly and a controller. The sleeve member is for sleeving onto a glans of a penis and has a guiding hole to be registered with an external urethral orifice of the glans. The conveying assembly includes a casing removably mounted to the sleeve member, and a conveying mechanism for advancing the urinary catheter to the guiding hole such that the urinary catheter is inserted into the external urethral orifice. The controller controls the conveying mechanism to advance the urinary catheter to the guiding hole. A urinary catheterization system and a method of using the urinary catheterization system are also disclosed.

公开(公告)号：US20130137034A1

公开(公告)日：2013-05-30

申请号：US13365660

申请日：2012-02-03

Applicant: Chi-Hua FU ,  Chung-Cheng WANG

Inventor： Chi-Hua FU ,  Chung-Cheng WANG

IPC: G03F7/004 ,  B08B3/04

CPC classification number: G03F7/16 ,  B08B3/00 ,  B08B3/02 ,  B08B7/00 ,  B08B7/04 ,  G03F7/091 ,  G03F7/094 ,  G03F7/095

Abstract: A method for pre-treating a wafer surface before applying a material thereon. The method includes positioning the wafer on a rotating apparatus. The wafer is rotated at a first rotational speed between about 50 revolutions per minute (rpm) and about 300 rpm and for a period of about 1 second to about 10 seconds while dispensing a cleaning solvent on the wafer surface. The wafer is rotated at a second rotational speed between about 500 rpm and about 1,500 rpm for a period of about 1 second to about 10 seconds. The wafer is then rotated at a third rotational speed between about 50 rpm and about 300 rpm for a period of about 1 second to about 5 seconds. With the wafer rotating at the third rotational speed, a solvent-containing material is thereafter deposited on the surface of the wafer.

Abstract translation: 一种在施加材料之前预处理晶片表面的方法。 该方法包括将晶片定位在旋转装置上。 以约50转/分钟（rpm）和约300rpm之间的第一旋转速度旋转晶片，并且在晶片表面上分配清洁溶剂约1秒至约10秒的时间。 晶片以约500rpm至约1500rpm之间的第二转速旋转约1秒至约10秒的时间。 然后将晶片以约50rpm至约300rpm之间的第三转速旋转约1秒至约5秒的时间。 随着晶片以第三转速旋转，此后在晶片的表面上沉积含溶剂的材料。

公开(公告)号：US20100294542A1

公开(公告)日：2010-11-25

申请号：US12852458

申请日：2010-08-07

Applicant: CHUNG-CHENG Wang

Inventor： CHUNG-CHENG Wang

IPC: H05K1/00

CPC classification number: H01L23/49805 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator, a conductive element(s) and a conductive material(s), wherein the conductive element embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, wherein the upper surface of conductive element is below the upper surface of insulator and is plated by the conductive material, meanwhile the conductive element include a protruding portion which is protruded the insulator, in this manner, solder balls are not needed, moreover the conductive element can further include an extending portion; the present invention may be capable of affording a thinner electrical device thickness and enhanced reliability.

Abstract translation: 公开了用于电气设备的基板。 用于由绝缘体，导电元件和导电材料组成的衬底的实施例，其中嵌入绝缘体中的导电元件和暴露于绝缘体的两个表面的两个表面用于电连接 其中导电元件的上表面在绝缘体的上表面下方并被导电材料电镀，同时导电元件包括​​突出绝缘体的突出部分，以这种方式不需要焊球，此外， 导电元件还可以包括延伸部分; 本发明可以提供更薄的电气装置厚度和增强的可靠性。

公开(公告)号：US07301415B2

公开(公告)日：2007-11-27

申请号：US11164924

申请日：2005-12-12

Applicant: Chung-Cheng Wang ,  Chao-Shi Chuang ,  Wen-Shih Lu ,  Yu-Chang Chen

Inventor： Chung-Cheng Wang ,  Chao-Shi Chuang ,  Wen-Shih Lu ,  Yu-Chang Chen

IPC: H03B1/00

CPC classification number: H03L7/10

Abstract: A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.

Abstract translation: 公开了一种适用于具有非常有限的初始频率锁定时间的多频带VCO无线系统的锁相环中的自动频率调谐方法。 选择较大的VCO组中的VCO的预定子集用作内插点。 内插点VCO以预定电压进行预校准，并且每个内插点VCO的最终产生的频率作为（频率，VCO）对存储到存储器中，对于每个内插点VCO为一对。 当给系统给出期望的频率时，通过使用用于跟踪和锁定的两个最相邻插值点的（频率，VCO）对进行插值来选择适当的VCO。

公开(公告)号：US07047146B2

公开(公告)日：2006-05-16

申请号：US10707519

申请日：2003-12-19

Applicant: Chao-Shi Chuang ,  Chung-Cheng Wang ,  Wen-Shih Lu

Inventor： Chao-Shi Chuang ,  Chung-Cheng Wang ,  Wen-Shih Lu

IPC: G01R35/00 ,  G06F19/00

CPC classification number: H03L7/113 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/199

Abstract: A PLL includes a loop filter for accumulating charge to generate a loop-filter voltage and a VCO having a plurality of frequency ranges. The VCO receives the loop-filter voltage and generates an output signal having a frequency according to the loop-filter voltage and a currently selected VCO frequency range. During PLL calibration, the loop-filter is connected to a constant voltage source; the PLL feedback signal is synchronized with the reference signal; a linear search, a binary search, or a memory lookup is used to find a first and a second VCO frequency range; first and second time durations are measured for the time durations between the second rising edges of the reference signal and the PLL feedback signal for the two VCO frequency ranges, and the optimal VCO frequency range is determined by setting the VCO frequency range to be the VCO frequency range having the shortest measured time duration.

Abstract translation: PLL包括用于累积电荷以产生环路滤波器电压的环路滤波器和具有多个频率范围的VCO。 VCO接收环路滤波器电压，并产生具有根据环路滤波器电压和当前选择的VCO频率范围的频率的输出信号。 在PLL校准期间，环路滤波器连接到恒定电压源; PLL反馈信号与参考信号同步; 使用线性搜索，二进制搜索或存储器查找来找到第一和第二VCO频率范围; 对于参考信号的第二上升沿和两个VCO频率范围的PLL反馈信号之间的持续时间测量第一和第二持续时间，并且通过将VCO频率范围设置为VCO来确定最佳VCO频率范围 频率范围具有最短的测量持续时间。

公开(公告)号：US6150892A

公开(公告)日：2000-11-21

申请号：US182236

申请日：1998-10-30

Applicant: Chen-Yi Lee ,  Terng-Yin Hsu ,  Bai-Jue Shieh ,  Chung Cheng Wang

Inventor： Chen-Yi Lee ,  Terng-Yin Hsu ,  Bai-Jue Shieh ,  Chung Cheng Wang

IPC: H03L7/085 ,  H03L7/095 ,  H03L7/099 ,  H03L7/18 ,  H03L7/00

CPC classification number: H03L7/0805 ,  H03L7/085 ,  H03L7/0997 ,  H03L7/18 ,  H03L2207/50 ,  H03L7/095

Abstract: A method and device for frequency synthesizing, in which the digital frequency synthesizer includes a clock pair having two similar ring-oscillators to separately generate a search frequency and an output frequency, a frequency tracking unit, and a clock controlling unit. The frequency-search method includes two stages: one stage is the coarse search stage based on the "Prune-and-Search", and other stage is the fine search stage based on the "fixed-step" algorithm. In order to determine which search scheme is used to search the target frequency and to determine the lock status, two cost functions for search and lock-in are derived. These two cost functions define the search threshold and the lock threshold, and these thresholds define the cost window and the lock window. If the frequency error is higher than both the search and lock thresholds, a coarse search is activated to estimate the correct frequency. And only when the frequency error falls between the search and the lock thresholds, should the fine search be activated. By properly assigning these two thresholds, the search performance, such as tinting and frequency error, and the output resolution can be improved. The digital frequency synthesizer which can be designed at HDL level and synthesized as part of a target cell library.

Abstract translation: 一种用于频率合成的方法和装置，其中数字频率合成器包括具有两个类似的环形振荡器以分别产生搜索频率和输出频率的时钟对，频率跟踪单元和时钟控制单元。 频率搜索方法包括两个阶段：一阶段是基于“剪枝搜索”的粗搜索阶段，其他阶段是基于“固定步长”算法的精细搜索阶段。 为了确定哪个搜索方案用于搜索目标频率并确定锁定状态，导出用于搜索和锁定的两个成本函数。 这两个成本函数定义搜索阈值和锁定阈值，并且这些阈值定义了成本窗口和锁定窗口。 如果频率误差高于搜索和锁定阈值，则会激活粗略搜索以估计正确的频率。 只有当频率误差落在搜索和锁定阈值之间时，才能激活精细搜索。 通过适当地分配这两个阈值，可以提高诸如着色和频率误差之类的搜索性能以及输出分辨率。 数字频率合成器，可以在HDL级别设计，并作为目标单元库的一部分合成。

公开(公告)号：US5821725A

公开(公告)日：1998-10-13

申请号：US731461

申请日：1996-10-16

Applicant: Chung-Cheng Wang ,  Jin-Chern Chiou ,  Shih-Tung Cheng

Inventor： Chung-Cheng Wang ,  Jin-Chern Chiou ,  Shih-Tung Cheng

IPC: H02P6/10 ,  H02P5/28

CPC classification number: H02P6/10

Abstract: An electric current compensation circuit for use with a multiple-phase burshless motor to reduce ripples in the output torque is disclosed. It contains a plurality of electric current compensation loops each for a respective phase winding and each of the electric compensation loops contains: (a) a first input for receiving a line current from the driver; (b) a second input for receiving the compensation current from the motor sensor; (c) a forward rectifying circuit for forwardly rectifying the line current and the compensation current; (d) a reverse rectifying circuit for reversely rectifying the line current and the compensation current; and (e) a summation circuit for summing the forwardly rectified compensation current and the reversely rectified compensation current and outputting a synthetic current to a phase winding of the motor. Each time the phase is changed, the electric current compensation circuit is triggered causing the synthetic current to be sent to the motor to allow the motor to generate an output torque with reduced ripple.

Abstract translation: 公开了一种与多相无刷电机一起使用以减少输出转矩波纹的电流补偿电路。 它包含多个电流补偿回路，每个电流补偿回路各自用于各自的相绕组，并且每个电补偿回路包含：（a）用于接收来自驾驶员的线电流的第一输入; （b）用于从电动机传感器接收补偿电流的第二输入; （c）正向整流线路电流和补偿电流的正向整流电路; （d）用于反向整流线路电流和补偿电流的反向整流电路; 和（e）用于将前向整流补偿电流和逆整流补偿电流相加的求和电路，并将合成电流输出到电动机的相绕组。 每次相位改变时，触发电流补偿电路，使得合成电流被发送到电动机，以允许电动机产生具有减小的纹波的输出转矩。