公开(公告)号：US20110193197A1

公开(公告)日：2011-08-11

申请号：US12700841

申请日：2010-02-05

Applicant: MUKTA G. FAROOQ ,  JOHN A. GRIESEMER ,  WILLIAM F. LANDERS ,  IAN D. MELVILLE ,  THOMAS M. SHAW ,  HUILONG ZHU

Inventor： MUKTA G. FAROOQ ,  JOHN A. GRIESEMER ,  WILLIAM F. LANDERS ,  IAN D. MELVILLE ,  THOMAS M. SHAW ,  HUILONG ZHU

IPC: H01L23/58 ,  H01L21/768 ,  H01L21/98

CPC classification number: H01L23/5226 ,  H01L21/2007 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.

Abstract translation: 公开了一种用于防止裂纹传播到3D集成电路的有源区域的结构，例如由薄化的衬底层或接合层的外围处的缺陷引发的裂纹及其形成方法。

公开(公告)号：US20110079907A1

公开(公告)日：2011-04-07

申请号：US12573183

申请日：2009-10-05

Applicant: MUKTA G. FAROOQ ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

Inventor： MUKTA G. FAROOQ ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.

Abstract translation: 公开了一种半导体器件，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在另一实施例中，在绝缘层和铜插塞之间也可以有铝层。 还公开了制造半导体器件的方法。

公开(公告)号：US07867887B2

公开(公告)日：2011-01-11

申请号：US12174074

申请日：2008-07-16

Applicant: Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

Inventor： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

IPC: H01L21/768

CPC classification number: H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

Abstract translation: 本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。 在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。 通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

公开(公告)号：US20090032909A1

公开(公告)日：2009-02-05

申请号：US11833348

申请日：2007-08-03

Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC: H01L23/58 ,  H01L21/64

CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

Abstract translation: 结构及其形成方法。 该结构包括半导体衬底，半导体衬底上的晶体管和半导体衬底顶部的N个互连层，N为正整数。 晶体管电耦合到N个互连层。 该结构还包括在N个互连层的顶部上的第一介电层和在第一介电层的顶部上的P个裂纹停止区，P是正整数。 该结构还包括在第一电介质层的顶部上的第二电介质层。 P裂纹停止区域的每个裂纹停止区域被第一介电层和第二介电层完全包围。 该结构还包括在第二电介质层的顶部上的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。

公开(公告)号：US20090015285A1

公开(公告)日：2009-01-15

申请号：US11776114

申请日：2007-07-11

Applicant: Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

Inventor： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

IPC: G01R31/26 ,  H01L21/4763 ,  H01L23/58

CPC classification number: G01R31/2853 ,  H01L22/34 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012

Abstract: Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad.

Abstract translation: 提供电气检测BEOL故障的测试结构。 在一个实施例中，该结构包括：输入/输出连接，其布置在嵌入绝缘体中的主导电垫上方; 设置在绝缘体上的电介质层; 主通孔延伸穿过介电层到主导电焊盘，用于在输入/输出连接和主导电焊盘之间提供电连接; 以及填充有与所述输入/输出连接电连接的导电材料的次级通孔，所述次级通孔延伸穿过所述电介质层到与所述主导电焊盘绝缘的次级导电焊盘电连接的次互连。

公开(公告)号：US07470985B2

公开(公告)日：2008-12-30

申请号：US11461208

申请日：2006-07-31

Applicant: Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

Inventor： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

Abstract translation: 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。

公开(公告)号：US20080150087A1

公开(公告)日：2008-06-26

申请号：US11615236

申请日：2006-12-22

Applicant: Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

Inventor： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

IPC: H01L23/544 ,  H01L21/00

CPC classification number: H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

Abstract translation: 本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。 半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。 一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

公开(公告)号：US20080038913A1

公开(公告)日：2008-02-14

申请号：US11463642

申请日：2006-08-10

Applicant: Mukta G. Farooq ,  Robert Hannon ,  Ian D. Melville ,  Kevin S. Petrarca ,  Donna S. Zupanski-Nielsen

Inventor： Mukta G. Farooq ,  Robert Hannon ,  Ian D. Melville ,  Kevin S. Petrarca ,  Donna S. Zupanski-Nielsen

IPC: H01L21/44

CPC classification number: H01L24/02 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/48

Abstract: Methods of forming an aluminum-free wire bond pad and the pad so formed are disclosed. In one embodiment, the method includes forming an opening through a dielectric layer to a last metal of a chip; forming a tantalum nitride (TaN) layer over the chip and over the opening; removing the tantalum nitride (TaN) layer outside of the opening; forming a passivation mask layer over the chip including a passivation mask opening over the last metal; forming a titanium tungsten (TiW) layer and a copper (Cu) layer over the chip; forming a mask layer over the chip including a mask opening to the copper (Cu) layer over the last metal; forming a nickel (Ni) layer and a copper (Cu) layer and then a gold (Au) layer in the mask opening; and removing the mask.

Abstract translation: 公开了形成无铝线接合焊盘和如此形成的焊盘的方法。 在一个实施例中，该方法包括通过电介质层形成开口至芯片的最后一个金属; 在芯片上并在开口上形成氮化钽（TaN）层; 去除开口外面的氮化钽（TaN）层; 在所述芯片上形成钝化掩模层，其包括在最后一个金属上的钝化掩模开口; 在芯片上形成钛钨（TiW）层和铜（Cu）层; 在所述芯片上形成掩模层，所述掩模层包括在最后金属上的铜（Cu）层的掩模开口; 在掩模开口中形成镍（Ni）层和铜（Cu）层，然后形成金（Au）层; 并取下面罩。

公开(公告)号：US20080023827A1

公开(公告)日：2008-01-31

申请号：US11461208

申请日：2006-07-31

Applicant: Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

Inventor： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC: H01L23/48

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

公开(公告)号：US08859390B2

公开(公告)日：2014-10-14

申请号：US12700841

申请日：2010-02-05

Applicant: Mukta G Farooq ,  John A Griesemer ,  William F Landers ,  Ian D Melville ,  Thomas M Shaw ,  Huilong Zhu

Inventor： Mukta G Farooq ,  John A Griesemer ,  William F Landers ,  Ian D Melville ,  Thomas M Shaw ,  Huilong Zhu

IPC: H01L23/58 ,  H01L25/065 ,  H01L21/78 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/20

CPC classification number: H01L23/5226 ,  H01L21/2007 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.

Abstract translation: 公开了一种用于防止裂纹传播到3D集成电路的有源区域的结构，例如由薄化的衬底层或接合层的外围处的缺陷引发的裂纹及其形成方法。