公开(公告)号：US07859073B2

公开(公告)日：2010-12-28

申请号：US12166810

申请日：2008-07-02

申请人： Mie Matsuo ,  Yusuke Kohyama

发明人： Mie Matsuo ,  Yusuke Kohyama

IPC分类号： H01L31/0203

CPC分类号： H01L27/14618 ,  H01L24/24 ,  H01L27/1464 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.

摘要翻译： 本发明提供了一种固态摄像装置，包括：设置在半导体衬底上的摄像像素部分，其中配置有多个具有光电转换元件和场效应晶体管的像素;以及外围电路 图像拾取像素部分。 驱动图像拾取像素部中的场效应晶体管的互连层形成在半导体衬底的第一表面侧上。 光电转换元件的光接收表面位于半导体衬底的第二表面侧。 固态摄像装置包括从半导体衬底的第二表面侧露出的第一端子和与第一端子电连接并可连接到半导体衬底的第一表面侧上的外部器件的第二端子。

公开(公告)号：US07507634B2

公开(公告)日：2009-03-24

申请号：US11812490

申请日：2007-06-19

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764 ,  H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US07235456B2

公开(公告)日：2007-06-26

申请号：US11340594

申请日：2006-01-27

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764 ,  H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US07095112B2

公开(公告)日：2006-08-22

申请号：US10664150

申请日：2003-09-17

申请人： Mitsuyoshi Endo ,  Mie Matsuo ,  Chiaki Takubo

发明人： Mitsuyoshi Endo ,  Mie Matsuo ,  Chiaki Takubo

IPC分类号： H01L23/48 ,  H05K7/02 ,  H01L27/02

CPC分类号： H01L23/66 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.

摘要翻译： 提供一种半导体器件，包括：布线板; 半导体芯片，其具有电连接到所述布线板上的布线的焊盘; 第二半导体芯片，其设置在面对半导体芯片的一侧的位置处的布线板上，其中集成有无源元件，并且具有用于外部连接的焊盘，无源元件的两端分别连接到该衬垫，并且其中至少一个是 电连接到电连接到半导体芯片的焊盘的布线板上的布线。

公开(公告)号：US20060102290A1

公开(公告)日：2006-05-18

申请号：US11221763

申请日：2005-09-09

申请人： Susumu Harada ,  Chiaki Takubo ,  Kenji Takahashi ,  Hideo Aoki ,  Hideo Numata ,  Hisashi Kaneko ,  Hirokazu Ezawa ,  Mie Matsuo ,  Hiroshi Ikenoue ,  Ichiro Omura

发明人： Susumu Harada ,  Chiaki Takubo ,  Kenji Takahashi ,  Hideo Aoki ,  Hideo Numata ,  Hisashi Kaneko ,  Hirokazu Ezawa ,  Mie Matsuo ,  Hiroshi Ikenoue ,  Ichiro Omura

IPC分类号： B32B37/00

CPC分类号： H01L21/6835 ,  H01L21/76898

摘要： A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.

摘要翻译： 晶片支撑板由可以渗透紫外线并具有近似圆盘形状的玻璃或树脂形成。 晶片支撑板的外径大于被支撑的半导体晶片的外径。 在晶片支撑板中，形成多个开口以对应于半导体晶片的多个通孔。 开口具有比通孔的开口面积大的开口面积，即具有较大的直径。

公开(公告)号：US07019364B1

公开(公告)日：2006-03-28

申请号：US09650748

申请日：2000-08-30

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US20050014311A1

公开(公告)日：2005-01-20

申请号：US10902391

申请日：2004-07-30

申请人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

发明人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065 ,  H01L25/10 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L29/40

CPC分类号： H01L23/642 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00

摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

摘要翻译： 公开了一种多芯片半导体器件，其中堆叠芯片，每个芯片包括形成在顶部的半导体衬底和电路部件，以及形成在半导体衬底的顶部上的层间绝缘膜。 至少一个芯片具有穿过半导体衬底和层间绝缘膜的通孔中形成的金属的连接插头。 具有连接插头的芯片通过该连接插头与另一个芯片电连接。

公开(公告)号：US5607718A

公开(公告)日：1997-03-04

申请号：US300127

申请日：1994-09-02

申请人： Yasutaka Sasaki ,  Mie Matsuo ,  Rempei Nakata ,  Junichi Wada ,  Nobuo Hayasaka ,  Hiroyuki Yano ,  Haruo Okano

发明人： Yasutaka Sasaki ,  Mie Matsuo ,  Rempei Nakata ,  Junichi Wada ,  Nobuo Hayasaka ,  Hiroyuki Yano ,  Haruo Okano

IPC分类号： B24B37/015 ,  B24B49/14 ,  B24B57/02 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  B05D5/12 ,  C03C15/00 ,  H01L21/465

CPC分类号： B24B37/015 ,  B24B57/02 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/7684

摘要： This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.

摘要翻译： 本发明提供了一种抛光方法，包括以下步骤：在其表面上具有凹陷部分的基底上形成待研磨的膜，以便至少填充凹部，并且通过在凹部中选择性地将被抛光的膜留在后面 通过使用含有研磨粒子和溶剂的研磨剂，pH为7.5以上来研磨该膜。 本发明还提供了一种抛光装置，其包括：用于存储抛光剂的抛光剂储存容器，用于抛光待抛光对象物的转盘，用于将抛光剂从抛光剂储存容器供应到转台上的抛光剂供给管， 抛光对象保持夹具，用于保持待抛光对象物，使被处理物体的表面与转盘相对;抛光剂供给管温度调节单元，连接到抛光剂供应管，用于调节抛光温度 代理商

公开(公告)号：US07608537B2

公开(公告)日：2009-10-27

申请号：US11861087

申请日：2007-09-25

申请人： Mie Matsuo ,  Hisashi Kaneko

发明人： Mie Matsuo ,  Hisashi Kaneko

IPC分类号： G03F7/00 ,  H01J49/42

CPC分类号： H01L21/76885 ,  G03F9/708 ,  G03F9/7084 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming an opening in a first film, embedding an alignment mark material for alignment with an upper layer in the opening, forming a second film on the first film in which the alignment mark material is embedded, irradiating the second film formed in a predetermined region including a position where the alignment mark material is embedded with a processing light, thereby to remove the second film to an extent that a portion of the second film remains in the predetermined region, and exposing the portion of the second film remaining in the predetermined region to an etching environment for etching the second film.

摘要翻译： 一种制造半导体器件的方法，包括在第一膜中形成开口，在开口中嵌入用于与上层对准的对准标记材料，在其中嵌入对准标记材料的第一膜上形成第二膜，照射 所述第二膜形成在包括所述对准标记材料被嵌入处理光的位置的预定区域中，从而将所述第二膜移除到所述第二膜的一部分保留在所述预定区域中的程度， 所述第二膜保留在所述预定区域中以蚀刻所述第二膜的蚀刻环境。

公开(公告)号：US20090003103A1

公开(公告)日：2009-01-01

申请号：US12142278

申请日：2008-06-19

申请人： Yuui SHIMIZU ,  Shigeo Ohshima ,  Mie Matsuo

发明人： Yuui SHIMIZU ,  Shigeo Ohshima ,  Mie Matsuo

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/145 ,  G11C5/04 ,  G11C5/066 ,  G11C5/143 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

摘要翻译： 提供半导体器件，半导体存储器测试器和多芯片封装。 半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。