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    Coolant service monitoring system
    11.
    发明申请
    Coolant service monitoring system 审中-公开
    冷却液服务监控系统

    公开(公告)号：US20050034510A1

    公开(公告)日：2005-02-17

    申请号：US10638462

    申请日：2003-08-12

    Applicant: Charlie Han

    Inventor： Charlie Han

    IPC: F01P11/06 ,  F01P11/14 ,  G01N33/00 ,  G01N27/27 ,  G01N31/00

    CPC classification number: F01P11/14 ,  F01P2011/066 ,  F01P2025/00 ,  F01P2025/80 ,  F01P2031/00

    Abstract: Engine coolant and its related components is a vital fluid in any internal combustion engine, however it is one of the most neglected systems in the vehicle. The newest domestic automobiles do not have service indicators for engine coolant; which would allow the owner to service the fluid before any serious damage occurs from electrolysis and metal breakdown. The proposed Coolant Service Monitoring System (CSMS) will utilize sensors to monitor the pH of the coolant mixture, as well as the DC voltage of the coolant with respect to ground. By monitoring the pH and voltage, the sensors can notify the operator when unsafe coolant conditions are present. Ultimately, by preventing excessive corrosion and accelerated electrolysis, automobile owners can save hundreds if not thousands of dollars by not having to replace heater cores, expensive radiators, and water pumps with the CSMS implemented in the vehicle.

    Abstract translation: 发动机冷却液及其相关组件是任何内燃机中重要的流体，但它是车辆中被忽视的系统之一。 国内最新的汽车没有发动机冷却液的服务指标; 这将允许业主在电解和金属破坏发生严重损坏之前对流体进行维修。 所提出的冷却液服务监控系统（CSMS）将利用传感器来监测冷却剂混合物的pH以及冷却剂相对于地面的直流电压。 通过监测pH和电压，当不安全的冷却液条件存在时，传感器可以通知操作员。 最终，通过防止过度腐蚀和加速电解，汽车业主可以通过在车辆中实施CSMS而不必更换加热器芯，昂贵的散热器和水泵来节省数百甚至数千美元。

    Alternate timing wafer burn-in method
    13.
    发明授权
    Alternate timing wafer burn-in method 有权
    替代定时晶片老化方法

    公开(公告)号：US06388460B1

    公开(公告)日：2002-05-14

    申请号：US09698713

    申请日：2000-10-27

    Applicant: Walx Fang ,  Charlie Han

    Inventor： Walx Fang ,  Charlie Han

    IPC: G01F3102

    CPC classification number: G01R31/318511 ,  G01R31/2879 ,  G01R31/318505 ,  G11C29/006 ,  G11C29/56012 ,  G11C2029/1204

    Abstract: An alternate-timing burn-in method suitable for testing a plurality of memory units on a wafer and capable of preventing any idling due to direct current timing. A first bit line voltage clocking signal is generated and sent to one terminal of any memory unit. A second bit line voltage clocking signal is generated and sent to the other terminal of the same memory unit. In addition, the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.

    Abstract translation: 一种适用于测试晶片上的多个存储器单元并且能够防止由于直流定时引起的空转的替代定时老化方法。 产生第一位线电压计时信号并将其发送到任何存储器单元的一个端子。 产生第二位线电压时钟信号并将其发送到同一存储器单元的另一端。 此外，第二位线电压计时信号的边沿对应于第一位线电压计时信号的中点。

    Cascade-type chip module
    15.
    发明授权
    Cascade-type chip module 有权
    级联型芯片模块

    公开(公告)号：US6166444A

    公开(公告)日：2000-12-26

    申请号：US337708

    申请日：1999-06-21

    Applicant: Min-Chih Hsuan ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Charlie Han

    IPC: H01L25/065 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L29/40

    CPC classification number: H01L25/0652 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/013

    Abstract: A cascade-type chip module. A laminate substrate having contacts is provided. Chips suitable for the cascade-type module are provided. Each chip includes a redistribution layer having a first region and a second region and bump contacts over the redistribution layer. A layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrical to the layout of those coupling with the second region of the redistribution layer, and each of the bump contacts coupling with the first region is coupled with a corresponding bump contact coupling with the second region through the redistribution layer. The chips are divided into a first group and a second group; the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group. The chips are coupled to each other by bumps. The chips are attached to the laminate substrate and the first group and the second group are respectively coupled with the contacts by two film carriers.

    Abstract translation: 级联型芯片模块。 提供具有触点的层叠基板。 提供了适用于级联型模块的芯片。 每个芯片包括具有第一区域和第二区域的再分配层，并且凸块接触再分布层上方。 与再分布层的第一区域耦合的突起触点的布局是与再分布层的第二区域耦合的布局的布局旋转对称的图像，并且与第一区域耦合的每个凸起触点与 通过再分布层与第二区域相应的凸起接触。 芯片分为第一组和第二组; 第一组堆叠在第二组上，使得第一组的每个芯片的第一区域与第二组的每个芯片的第二区域对准，并且第一组的每个芯片的第二区域与第一组的第一组对准 第二组的每个芯片的区域。 芯片通过凸块相互耦合。 芯片附接到层叠基板，第一组和第二组分别通过两个薄膜载体与触点耦合。

    Method for burn-in operation on a wafer of memory devices
    16.
    发明授权
    Method for burn-in operation on a wafer of memory devices 失效
    用于存储器件晶片上的老化操作的方法

    公开(公告)号：US5946248A

    公开(公告)日：1999-08-31

    申请号：US32401

    申请日：1998-02-27

    Applicant: Pien Chien ,  Shih-Chin Lin ,  Charlie Han

    Inventor： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

    IPC: G01R31/28 ,  G11C29/50 ,  G11C13/00

    CPC classification number: G11C29/50 ,  G01R31/2856 ,  G11C11/401

    Abstract: A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

    Abstract translation: 提供一种在形成有多个骰子的晶片上使用的方法，每个骰子上具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过这种方法，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

    Three dimensional geometrical puzzle
    17.
    发明申请
    Three dimensional geometrical puzzle 审中-公开
    三维几何拼图

    公开(公告)号：US20060061033A1

    公开(公告)日：2006-03-23

    申请号：US10947452

    申请日：2004-09-22

    Applicant: Charlie Han

    Inventor： Charlie Han

    IPC: A63F9/08

    CPC classification number: A63F9/083 ,  A63F9/0857 ,  A63F2009/0815 ,  A63F2009/0888

    Abstract: A handheld puzzle is described. The puzzle reduces friction between moveable pieces and at the same time allows for restrained alignment of the moveable pieces. An inner core of the puzzle can be adapted for use with a plurality of outer moveable face pieces that can comprise a variety of surface geometries.

    Abstract translation: 描述了一个手持谜题。 该益智减少可移动件之间的摩擦，同时允许可移动件的限制对准。 拼图的内芯可以适用于可以包括各种表面几何形状的多个外部可移动的面部件。

    Preburn-in dynamic random access memory module and preburn-in circuit board thereof
    20.
    发明授权
    Preburn-in dynamic random access memory module and preburn-in circuit board thereof 失效
    Preburn-in动态随机存取存储器模块及其Preburn-in电路板

    公开(公告)号：US06279141B1

    公开(公告)日：2001-08-21

    申请号：US09434987

    申请日：1997-08-13

    Applicant: Min-Chih Hsuan ,  Charlie Han ,  Jerry Jaw ,  Tung-Chi Liu

    Inventor： Min-Chih Hsuan ,  Charlie Han ,  Jerry Jaw ,  Tung-Chi Liu

    IPC: G06F1750

    CPC classification number: G11C29/56016 ,  G11C11/401 ,  G11C29/48 ,  H05K1/0286 ,  H05K3/0052

    Abstract: A preburn-in DRAM module circuit board is provided, which allows a plurality of DRAM modules to be constructed directly thereon, and which can be directly connected to a large burn-in oven so as to perform a burn-in process concurrently on the DRAM modules mounted thereon to check for any defected IC chips that are to be reworked. After the burn-in process, each of the DRAM modules can be cut apart from the circuit board to serve as a single memory module. The preburn-in DRAM module circuit board allows the manufacturing process for the DRAM modules to be reduced in schedule and manufacturing cost. Material cost can also be saved since the burn-in circuit and the module circuit are arranged on the same circuit board.

    Abstract translation: 提供了一种预烧入式DRAM模块电路板，其允许在其上直接构建多个DRAM模块，并且其可以直接连接到大型老化炉，以便在DRAM上同时执行老化过程 安装在其上的模块，以检查要重新加工的任何缺陷的IC芯片。 在老化过程之后，可以将每个DRAM模块与电路板分开以用作单个存储器模块。 预烧入式DRAM模块电路板允许在时间表和制造成本上减少DRAM模块的制造过程。 由于老化电路和模块电路布置在同一电路板上，因此也可节省材料成本。

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