公开(公告)号：US20150287595A1

公开(公告)日：2015-10-08

申请号：US14725430

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy WEI ,  Mariappan HARIHARAPUTHIRAN ,  Dae Geun YANG ,  Dae-Han CHOI ,  Xiang HU ,  Richard J. CARTER ,  Akshey SEHGAL

IPC: H01L21/033 ,  H01L29/78 ,  H01L21/027

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US20150236133A1

公开(公告)日：2015-08-20

申请号：US14181790

申请日：2014-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Gopal SRINIVASAN ,  Amaury GENDRON

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/0629 ,  H01L29/785 ,  H01L29/94

Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

Abstract translation: 提供了用于形成具有更宽FinFET的半导体器件以用于变容二极管的较高可调性的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在所述半导体器件上施加间隔层; 蚀刻半导体器件以去除间隔层的至少一部分以暴露多个心轴; 去除心轴; 蚀刻半导体器件以去除电介质层的一部分; 形成至少一个翅片; 以及去除间隔层和电介质层。 一个中间半导体器件包括例如：衬底; 介电层; 形成在所述电介质层上的多个心轴，所述心轴包括第一组心轴和第二组心轴，其中所述第一组心轴的宽度是所述第二组心轴的两倍; 以及施加在心轴上的间隔层。

公开(公告)号：US20150115418A1

公开(公告)日：2015-04-30

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy WEI ,  Mariappan HARIHARAPUTHIRAN ,  Dae Geun YANG ,  Dae-Han CHOI ,  Xiang HU ,  Richard J. CARTER ,  Akshey SEHGAL

IPC: H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

公开(公告)号：US20180226294A1

公开(公告)日：2018-08-09

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David Michael PERMANA ,  Guillaume BOUCHE ,  Andy WEI ,  Mark ZALESKI ,  Anbu Selvam KM MAHALINGAM ,  Craig Michael CHILD, JR. ,  Roderick Alan AUGUR ,  Shyam PAL ,  Linus JANG ,  Xiang HU ,  Akshey SEHGAL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20160260701A1

公开(公告)日：2016-09-08

申请号：US15156750

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN ,  Manjunatha PRABHU ,  Anil KUMAR

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract translation: 这里提出了配置为ESD保护装置的场效应晶体管（FET）。 在一个实施例中，FET可以被配置为以快速恢复操作模式操作。 FET可以包括半导体衬底，形成在衬底上的栅极和形成在与栅极间隔开的衬底上的伪栅极。

公开(公告)号：US20160099344A1

公开(公告)日：2016-04-07

申请号：US14928057

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping LIU ,  Jing WAN ,  Andy WEI

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

公开(公告)号：US20160079168A1

公开(公告)日：2016-03-17

申请号：US14947259

申请日：2015-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hiroaki NIIMI ,  Kisik CHOI ,  Hoon KIM ,  Andy WEI ,  Guillaume BOUCHE

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

公开(公告)号：US20150333067A1

公开(公告)日：2015-11-19

申请号：US14812500

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Lun ZHAO ,  Dae Geun YANG ,  Jin Ping LIU ,  Tien-Ying LUO ,  Guillaume BOUCHE ,  Mariappan HARIHARAPUTHIRAN ,  Churamani GAIRE

IPC: H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

公开(公告)号：US20150263089A1

公开(公告)日：2015-09-17

申请号：US14206203

申请日：2014-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar SINGH ,  Andy WEI

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66136 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/735 ,  H01L29/785 ,  H01L29/8611

Abstract: A non-planar diode is fabricated, with an n- or p-type raised structure, such as a fin, coupled to the substrate. A well of an opposite type is located under the raised structure, along with an area having additional impurity, located directly under the raised structure, and within the well. This additional implant creates a p-n junction within the substrate, the non-planar diode having an ideality factor in a range of 1 to about 1.05.

Abstract translation: 制造非平面二极管，其具有耦合到衬底的n型或p型凸起结构，例如鳍。 相反类型的井位于升高的结构下方，以及具有附加杂质的区域，位于凸起结构的正下方以及井内。 该附加植入物在衬底内产生p-n结，该非平面二极管的理想因子在1至约1.05的范围内。