公开(公告)号：US20170154816A1

公开(公告)日：2017-06-01

申请号：US14954112

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean X. LIN ,  Ming HE ,  Frank SMITH ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L21/76885 ,  H01L21/32051 ,  H01L21/32133 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76892 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53261

Abstract: A method of fabricating amorphous metal interconnections includes forming an amorphous metal layer over a base insulating layer on a semiconductor device using an amorphous metal having a non-crystalline structure. A portion of the amorphous metal layer is selectively removed to form a three dimensional pattern within a remaining portion of the amorphous metal layer. A fill insulating layer is disposed over the remaining portion of the amorphous metal layer and base insulating layer to fill the three dimensional pattern to form amorphous metal interconnects between semiconductor devices.

公开(公告)号：US20160141489A1

公开(公告)日：2016-05-19

申请号：US14841997

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Xiuyu CAI ,  Seowoo NAM ,  Hyun-Jin CHO

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US20150372084A1

公开(公告)日：2015-12-24

申请号：US14309956

申请日：2014-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi QI ,  Xunyuan ZHANG ,  Catherine B. LABELLE

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract translation: 提供一种制造凸起翅片结构的方法，所述制造方法包括：在衬底上提供衬底和至少一个电介质层; 在所述至少一个电介质层中形成沟槽，所述沟槽具有下部，侧部和上部，所述上部至少部分地从所述下部向外偏移并且通过所述侧部与所述下部 一部分; 并且在沟槽中生长材料以形成凸起的翅片结构，其中形成沟槽以确保沟槽的下部中的任何生长缺陷终止于沟槽的下部或横向部分，并且不延伸 进入沟槽的上部。

公开(公告)号：US20190311948A1

公开(公告)日：2019-10-10

申请号：US16436117

申请日：2019-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LICAUSI ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

公开(公告)号：US20180130899A1

公开(公告)日：2018-05-10

申请号：US15343590

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/785 ,  H01L21/2251 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. Prior to deposition of the conductive material, source/drain contact structures are recessed and a selective etch is used to remove sidewall spacers that are disposed between the source/drain contacts and the gate structures.

公开(公告)号：US20180012798A1

公开(公告)日：2018-01-11

申请号：US15689413

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L23/535 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US20150371899A1

公开(公告)日：2015-12-24

申请号：US14310314

申请日：2014-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Sean X. LIN

IPC: H01L21/768 ,  H01L21/288

CPC classification number: H01L21/288 ,  C23C18/1834 ,  C23C18/40 ,  C23C18/405 ,  H01L21/76874 ,  H01L21/76877

Abstract: Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.

Abstract translation: 提供了电路结构制造方法，其包括：图案化设置在衬底结构上的电介质层内的至少一个开口; 在介电层的至少一个开口内提供衬垫材料; 在衬垫材料的至少一部分上设置表面活性剂; 以及使用无电镀方法在所述衬里材料上沉积导电材料以形成导电结构，并且所述设置的表面活性剂抑制在所述导电结构内形成空隙。

公开(公告)号：US20140370705A1

公开(公告)日：2014-12-18

申请号：US14473266

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan ZHANG ,  Xiuyu CAI

IPC: H01L21/321 ,  H01L21/283

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

公开(公告)号：US20140353805A1

公开(公告)日：2014-12-04

申请号：US13903618

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd RYAN ,  Moosung M. CHAE ,  Larry ZHAO ,  Kunaljeet TANWAR ,  Nicholas Vincent LICAUSI ,  Christian WITT ,  Ailian ZHAO ,  Ming HE ,  Sean X. LIN ,  Xunyuan ZHANG

IPC: H01L21/3105 ,  H01L23/00

CPC classification number: H01L21/02101 ,  H01L21/02063 ,  H01L21/76814

Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.

Abstract translation: 提供了用于从半导体器件去除污染物的方法，例如从超低k膜的孔中除去污染物。 一方面，一种方法包括：向电介质层提供含有污染物的孔，并将介电层暴露于超临界流体。 超临界流体可以溶解和去除污染物。 在另一方面，提供了一种中间半导体器件结构，其包含具有含污染孔的电介质层和孔内的超临界流体。 另一方面，提供了具有含有未污染孔的电介质层的半导体器件结构。

公开(公告)号：US20190279860A1

公开(公告)日：2019-09-12

申请号：US15916594

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shariq SIDDIQUI ,  Han YOU ,  Xunyuan ZHANG ,  Rohit GALATAGE ,  Roger A. QUON ,  Christopher J. PENNY

IPC: H01L21/02 ,  H01L49/02 ,  C23C16/455 ,  H01L27/06

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.