公开(公告)号：US20050135074A1

公开(公告)日：2005-06-23

申请号：US10744695

申请日：2003-12-23

Applicant: Gregory Dunn ,  Remy Chelini ,  Robert Croswell ,  Timothy Dean ,  Claudia Gamboa ,  Jovica Savic

Inventor： Gregory Dunn ,  Remy Chelini ,  Robert Croswell ,  Timothy Dean ,  Claudia Gamboa ,  Jovica Savic

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/42

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract translation: 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。

公开(公告)号：US20050079375A1

公开(公告)日：2005-04-14

申请号：US10682557

申请日：2003-10-09

Applicant: Timothy Dean ,  Gregory Dunn ,  Remy Chelini ,  Claudia Gamboa

Inventor： Timothy Dean ,  Gregory Dunn ,  Remy Chelini ,  Claudia Gamboa

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/38 ,  B32B3/00 ,  B32B15/00

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic release material (215). The conductive metal foil layer has an exposed surface (212) that is coated with a high temperature anti-oxidant barrier (220) and has a roughness less than 0.05 microns RMS. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the exposed surface of the conductive metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

Abstract translation: 在一个实施例中，可剥离电路板箔（200）具有通过无机剥离材料（215）粘合的金属支撑层（205）和导电金属箔层（210）。 导电金属箔层具有涂覆有高温抗氧化剂屏障（220）并具有小于0.05微米RMS的粗糙度的暴露表面（212）。 在第二实施例中，可剥离印刷电路箔（200）具有设置在导电金属箔层的暴露表面上的结晶的电介质氧化物层（405）和设置在结晶的电介质氧化物层上的电极层（415），形成 可以粘附到柔性或刚性电路板的层的介电可剥离电路板箔（400），之后金属支撑层可以被剥离，留下包括金属箔层，结晶化电介质氧化物层， 和电极层。

公开(公告)号：US20070151758A1

公开(公告)日：2007-07-05

申请号：US11323515

申请日：2005-12-30

Applicant: Gregory Dunn ,  Jaroslaw Magera ,  Jovica Savic

Inventor： Gregory Dunn ,  Jaroslaw Magera ,  Jovica Savic

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

Abstract translation: 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

公开(公告)号：US20070139294A1

公开(公告)日：2007-06-21

申请号：US11312286

申请日：2005-12-20

Applicant: Gregory Dunn ,  Robert Croswell ,  George Kumpf ,  John Svigelj

Inventor： Gregory Dunn ,  Robert Croswell ,  George Kumpf ,  John Svigelj

IPC: H01Q15/24

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates , wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

公开(公告)号：US20060137173A1

公开(公告)日：2006-06-29

申请号：US11021444

申请日：2004-12-23

Applicant: Gregory Dunn ,  Jovica Savic ,  John Svigelj ,  Nadia Yala

Inventor： Gregory Dunn ,  Jovica Savic ,  John Svigelj ,  Nadia Yala

IPC: H01P11/00 ,  H01K3/10

CPC classification number: H01Q9/0407 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49165

Abstract: A textured dielectric panel (305, 520, 625, 745, 925, 1035, 1205) is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a-second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel may be metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.

Abstract translation: 通过将第一掩模图案（310,510,610,710,915,1015,1210）施加到固体面板的第一侧来制造纹理化电介质面板（305,520,625,745,925,1035,1205） 由第一材料制成，其是陶瓷电介质，然后通过第一掩模图案从第一侧喷砂固体板，以至少部分地产生成型腔（315,920,1040）。 固体面板的成形腔可以填充有第二材料（330,740）。 第一和第二材料具有基本上不同的介电常数。 固体面板的第一面和第二面可以金属化（325），形成贴片天线。 通过使用额外的掩模和/或喷砂步骤，可使成形的空腔变得更加复杂。

公开(公告)号：US06256866B1

公开(公告)日：2001-07-10

申请号：US09309457

申请日：1999-05-11

Applicant: Gregory Dunn

Inventor： Gregory Dunn

IPC: H01C1728

CPC classification number: H05K1/167 ,  H01C1/14 ,  H01C7/005 ,  H01C17/281 ,  H05K1/095 ,  H05K3/0023 ,  H05K3/243 ,  H05K3/4664 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/49099 ,  Y10T29/49101 ,  Y10T29/49128 ,  Y10T29/49156

Abstract: A method of manufacturing a printed circuit board with a polymer thick-film (PTF) resistor whose dimensions can be defined with improved precision by providing a circuit board construction having a planar surface where the resistor is to be deposited. To achieve the desired board construction, the interconnect for the resistor is pattern plated using a permanent photodielectric layer as a plating mask instead of a sacrificial plating resist. The interconnect can be patterned before or after the PTF resistor ink is printed. The x and z dimensions (width and thickness, respectively) of the resistor are determined by the deposition process, while the y dimension (electrical length) is accurately determined by copper terminations.

公开(公告)号：US20060269728A1

公开(公告)日：2006-11-30

申请号：US11139056

申请日：2005-05-27

Applicant: Gregory Dunn ,  Remy Chelini ,  Timothy Dean

Inventor： Gregory Dunn ,  Remy Chelini ,  Timothy Dean

IPC: B32B3/00

CPC classification number: H05K3/025 ,  B32B7/06 ,  B32B9/00 ,  B32B9/041 ,  B32B15/00 ,  B32B15/043 ,  B32B15/20 ,  B32B2264/102 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/54 ,  B32B2307/546 ,  B32B2307/714 ,  B32B2457/08 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2203/0264 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic high temperature release structure (215) that comprises a co-deposited layer (250) and a metal oxide layer (260). The co-deposited layer comprises an admixture of nickel and one or more of boron, phosphorus, and chromium. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

Abstract translation: 在一个实施例中，可剥离电路板箔（200）具有通过包含共沉积层（250）的无机高温释放结构（215）结合的金属支撑层（205）和导电金属箔层（210） 和金属氧化物层（260）。 共沉积层包含镍和硼，磷和铬中的一种或多种的混合物。 在第二实施例中，可剥离印刷电路箔（200）具有设置在金属箔层上的结晶化电介质氧化物层（405）和设置在结晶化电介质氧化物层上的电极层（415），形成介电剥离电路板箔 （400），其可以粘附到柔性或刚性电路板的层上，之后金属支撑层可以被剥离，留下包括金属箔层，结晶的电介质氧化物层和电极层的电容结构。

公开(公告)号：US20050128720A1

公开(公告)日：2005-06-16

申请号：US10736327

申请日：2003-12-15

Applicant: Robert Croswell ,  Gregory Dunn ,  Robert Lempkowski ,  Aroon Tungare ,  Jovica Savic

Inventor： Robert Croswell ,  Gregory Dunn ,  Robert Lempkowski ,  Aroon Tungare ,  Jovica Savic

IPC: H01G20060101 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract translation: 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

公开(公告)号：US20050001316A1

公开(公告)日：2005-01-06

申请号：US10612590

申请日：2003-07-01

Applicant: Timothy Dean ,  Terance Blake ,  Gregory Dunn ,  Remy Chelini ,  William Lytle ,  Owen Fay ,  George Strumberger

Inventor： Timothy Dean ,  Terance Blake ,  Gregory Dunn ,  Remy Chelini ,  William Lytle ,  Owen Fay ,  George Strumberger

IPC: H01L23/485 ,  H01L23/48 ,  H01L21/44 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/48744

Abstract: The invention provides an integrated device with corrosion-resistant capped bond pads. The capped bond pads include at least one aluminum bond pad on a semiconductor substrate. A layer of electroless nickel is disposed on the aluminum bond pad. A layer of electroless palladium is disposed on the electroless nickel, and a layer of immersion gold is disposed on the electroless palladium. A capped bond pad and a method of forming the capped bond pads are also disclosed.

Abstract translation: 本发明提供了一种具有耐腐蚀的封盖焊盘的集成器件。 封装的接合焊盘包括半导体衬底上的至少一个铝接合焊盘。 在铝合金焊盘上设置一层无电镀镍。 在化学镀镍上设置一层无电镀钯，并在无电镀钯上设置一层浸金。 还公开了一种封盖接合焊盘和形成封盖接合焊盘的方法。

公开(公告)号：US06638872B1

公开(公告)日：2003-10-28

申请号：US10255881

申请日：2002-09-26

Applicant: Robert Croswell ,  Gregory Dunn

Inventor： Robert Croswell ,  Gregory Dunn

IPC: H01L21311

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/12 ,  H01L29/78603

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. Monocrystalline substrates having a hydrogen ion implant are cleaved along the hydrogen ion implant, and an insulating substrate is bonded to the monocrystalline oxide.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的单晶硅在单晶氧化物材料上的外延和外延生长。 具有氢离子注入的单晶衬底沿氢离子注入被切割，绝缘衬底与单晶氧化物结合。