公开(公告)号：US09397018B2

公开(公告)日：2016-07-19

申请号：US13742456

申请日：2013-01-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/373 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/06 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US20140151856A1

公开(公告)日：2014-06-05

申请号：US13693205

申请日：2012-12-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/34 ,  H01L21/56

CPC classification number: H01L23/34 ,  H01L21/56 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈r and the thermal conductivity λ of the insulation layer satisfy the condition λ·∈r

Abstract translation: 芯片模块包括载体，布置在载体上或嵌入载体内部的半导体芯片，以及至少部分覆盖载体的表面的绝缘层。 绝缘层的介电常数εr和热导率λ满足条件λ·∈r<4.0 W·m-1·K-1。

公开(公告)号：US10964628B2

公开(公告)日：2021-03-30

申请号：US16282207

申请日：2019-02-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10700037B2

公开(公告)日：2020-06-30

申请号：US15811375

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Eung San Cho ,  Thorsten Meyer ,  Xaver Schloegel ,  Thomas Behrens ,  Josef Hoeglauer

IPC: H01L23/00 ,  H01L23/498

Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

公开(公告)号：US20160064255A1

公开(公告)日：2016-03-03

申请号：US14935510

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。

公开(公告)号：US20150214133A1

公开(公告)日：2015-07-30

申请号：US14165754

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Teck Sim Lee ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/40 ,  H01L23/00 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/4006 ,  H01L21/31053 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.

Abstract translation: 电子设备包括半导体芯片，其包括电极，基板元件和将电极连接到基板元件的接触元件。 电子设备还包括密封剂，其被配置为使接触元件至少部分地暴露，使得散热器可以连接到接触元件。

公开(公告)号：US20150155271A1

公开(公告)日：2015-06-04

申请号：US14617797

申请日：2015-02-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Joachim Mahler ,  Johannes Lodermeyer

IPC: H01L25/00 ,  H01L21/768 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/071 ,  H01L25/072 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24135 ,  H01L2224/245 ,  H01L2224/40105 ,  H01L2224/40227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

Abstract translation: 一种器件包括具有第一接触焊盘的第一功率半导体芯片和第一面上的第二接触焊盘以及第二面上的第三接触焊盘。 该器件还包括具有第一接触焊盘的第二功率半导体芯片和第一面上的第二接触焊盘以及第二面上的第三接触焊盘。 第一功率半导体芯片和第二功率半导体芯片彼此重叠配置，第一功率半导体芯片的第一面朝向第二功率半导体芯片的第一面的方向。 此外，第一功率半导体芯片至少部分地位于第二功率半导体芯片的轮廓外侧。

公开(公告)号：US08853835B2

公开(公告)日：2014-10-07

申请号：US13645548

申请日：2012-10-05

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Chooi Mei Chong

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/488 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/37111 ,  H01L2224/37118 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15701 ,  H01L2924/15717 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract translation: 提供芯片封装。 芯片封装包括芯片载体，电压源引线，感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压源引线和感测端子。

公开(公告)号：US20140197552A1

公开(公告)日：2014-07-17

申请号：US13742456

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US11515244B2

公开(公告)日：2022-11-29

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.