公开(公告)号：US06720502B1

公开(公告)日：2004-04-13

申请号：US09571611

申请日：2000-05-15

申请人： David J. Alcoe ,  Francis J. Downes, Jr. ,  Gerald W. Jones ,  John S. Kresge ,  Cheryl L. Tytran-Palomaki

发明人： David J. Alcoe ,  Francis J. Downes, Jr. ,  Gerald W. Jones ,  John S. Kresge ,  Cheryl L. Tytran-Palomaki

IPC分类号： H01R1204

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0215 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2924/00

摘要： A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

公开(公告)号：US06559388B1

公开(公告)日：2003-05-06

申请号：US09328189

申请日：1999-06-08

申请人： John S. Kresge ,  Voya R. Markovich

发明人： John S. Kresge ,  Voya R. Markovich

IPC分类号： H05K100

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

摘要： An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a soldered interface, such as a solder ball or a solder column, between a chip carrier (or chip) and an electronic carrier such as a circuit card. The thermally induced strain may be caused during thermal cycling by a mismatch in coefficient of thermal expansion (CTE), and consequent differential rates in thermal expansion, between the chip carrier (or chip) and the electronic carrier. The thermally induced strain may also exist with a large chip carrier characterized by a large temperature difference during thermal transients between the electronic carrier and localized regions of the chip carrier, even in the absence of a CTE mismatch. The electrical structure of the present invention includes an interposing compliant layer of soft and spongy material between the chip carrier (or chip) and the electronic carrier. Thermal strains resulting from the differential rates of thermal expansion are diverted from the soldered interface into small motions of material within the compliant layer.

摘要翻译： 一种用于减小芯片载体（或芯片）和电子载体（例如电路卡）之间的焊接界面（例如焊球或焊料柱）中的热诱导应变的电结构和相关制造方法。 在热循环期间可能由热膨胀系数（CTE）失配引起的热诱导应变，以及随之而来的芯片载体（或芯片）和电子载体之间的热膨胀差速率。 即使在没有CTE不匹配的情况下，热诱导应变也可以存在于具有在电子载体和芯片载体的局部区域之间的热瞬变期间具有大的温度差的大芯片载体。 本发明的电气结构包括在芯片载体（或芯片）和电子载体之间的柔软和海绵状材料的插入顺应层。 由不同的热膨胀率导致的热应变从焊接界面转移到顺应层内的材料的小运动中。

公开(公告)号：US06341071B1

公开(公告)日：2002-01-22

申请号：US09272517

申请日：1999-03-19

申请人： Eric A. Johnson ,  John S. Kresge

发明人： Eric A. Johnson ,  John S. Kresge

IPC分类号： H05K111

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00

摘要： A method and structure for reducing thermally induced strains on the solder joints that couple a ball grid array (BGA) module to a circuit card, so as to improve the fatigue life of the BGA module. The thermally induced strains arise from a mismatch in thermal expansion coefficient between the dielectric substrate of the BGA module and the dielectric board of the circuit card. The method generates void annular regions around portions of the BGA dielectric substrate to which the BGA solder balls are to be attached and/or around portions of the circuit card dielectric material to which the BGA module is to be attached. This results in the formation of dielectric islands or peninsulas that bound the solder balls of the BGA module after installation on the circuit card. The dielectric islands or peninsulas thus formed serve to increase the effective height over which the differential expansion is accommodated, thereby reducing the strains throughout the solder joints. Additionally, the void annular regions provide space for the deformation of the dielectric islands or peninsulas, thereby increasing their compliance and transferring strain from the solder joints to the dielectric islands or peninsulas.

摘要翻译： 一种用于减少将球栅阵列（BGA）模块耦合到电路卡的焊点上的热诱导应变的方法和结构，以提高BGA模块的疲劳寿命。 热诱导的应变来自BGA模块的电介质基板和电路卡的电介质板之间的热膨胀系数的不匹配。 该方法在BGA电介质基板周围产生空隙环形区域，BGA电介质基板将附着BGA焊球和/或围绕BGA模块所要连接的电路卡电介质材料的周围。 这导致在安装在电路卡上之后形成结合BGA模块的焊球的电介质岛或半岛。 这样形成的电介质岛或半岛用于增加容纳差动膨胀的有效高度，从而减少整个焊点的应变。 此外，空隙环形区域为介质岛或半岛的变形提供了空间，从而增加了它们的顺应性并将应变从焊点传递到电介质岛或半岛。

公开(公告)号：US5347710A

公开(公告)日：1994-09-20

申请号：US098485

申请日：1993-07-27

申请人： Thomas P. Gall ,  Howard L. Heck ,  John S. Kresge

发明人： Thomas P. Gall ,  Howard L. Heck ,  John S. Kresge

IPC分类号： H01L23/52 ,  G06F15/173 ,  G06F15/80 ,  H05K1/00 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/36

CPC分类号： H05K3/4635 ,  H05K3/462 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  Y10T29/49126 ,  Y10T29/49155

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。

公开(公告)号：US20080098595A1

公开(公告)日：2008-05-01

申请号：US11590888

申请日：2006-11-01

申请人： John S. Kresge ,  Cheryl L. Palomaki

发明人： John S. Kresge ,  Cheryl L. Palomaki

IPC分类号： H05K3/36

CPC分类号： H05K3/421 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of making a circuitized substrate in which pairs of vertically oriented though holes are formed such that at least one of the through holes is partially embedded within a lower one, thus assuring a sound connection following subsequent lamination or other steps the substrate including such holes is subjected to during manufacture. An electrical assembly including a substrate with such features is also provided.

摘要翻译： 一种制造电路化基板的方法，其中形成一对垂直取向的贯穿孔，使得至少一个通孔部分地嵌入下部通孔中，从而确保随后的层压或其它步骤之后的声音连接，所述基板包括这种孔 在制造过程中受到影响。 还提供了一种包括具有这种特征的基底的电组件。

公开(公告)号：US06998290B2

公开(公告)日：2006-02-14

申请号：US10715736

申请日：2003-11-18

申请人： Sylvia Adae-Amoakoh ,  John S. Kresge ,  Voya R. Markovich ,  Thurston B. Youngs, Jr.

发明人： Sylvia Adae-Amoakoh ,  John S. Kresge ,  Voya R. Markovich ,  Thurston B. Youngs, Jr.

IPC分类号： H01L21/44

CPC分类号： H05K3/4069 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/061 ,  H05K3/062 ,  H05K3/247 ,  H05K3/3484 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0305 ,  H05K2201/035 ,  H01L2224/0401

摘要： A method for forming a flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

摘要翻译： 一种用于形成具有非电镀接触焊盘的倒装芯片可连接衬底的方法。 衬底在具有内部接触面积的图案化内部金属层上的介电层上具有外部金属箔层。 选择内部接触区域上方的外部金属箔层的区域。 延伸到内部接触区域的微孔腔在所选择的区域内中心穿孔，并且填充有形成外部接触焊盘的导电浆料块。 外部接触焊盘用作蚀刻掩模以去除相邻的外部金属箔。

公开(公告)号：US06887779B2

公开(公告)日：2005-05-03

申请号：US10719495

申请日：2003-11-21

申请人： David J. Alcoe ,  Francis J. Downes, Jr. ,  Gerald W. Jones ,  John S. Kresge ,  Cheryl L. Tytran-Palomaki

发明人： David J. Alcoe ,  Francis J. Downes, Jr. ,  Gerald W. Jones ,  John S. Kresge ,  Cheryl L. Tytran-Palomaki

IPC分类号： H01L23/498 ,  H05K3/46 ,  H01L21/4763

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0215 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2924/00

摘要： A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

摘要翻译： 一种具有增加的芯片连接器和电镀通孔密度的半导体芯片载体。 特别地，其中具有多个电镀通孔的基板和其上的抗疲劳再分布层。 再分配层包括选择性地定位在电镀通孔上并接触电镀通孔的多个通孔。 所述基板还包括接地平面，两对信号面和两对电源层，其中所述第二对电源层位于所述外部电介质层的正下方。 衬底内埋入电镀通孔。

公开(公告)号：US06829823B2

公开(公告)日：2004-12-14

申请号：US10067551

申请日：2002-02-05

申请人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H01K310

CPC分类号： H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

摘要翻译： 一种制造多层互连结构的方法。 第一和第二导电构件分别形成在第一和第二电介质层上。 电介质层形成在导热层的相对表面上。 第一和第二导电层形成在第一介电层内。 第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。 通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。 形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

公开(公告)号：US06509546B1

公开(公告)日：2003-01-21

申请号：US09526034

申请日：2000-03-15

申请人： Frank D. Egitto ,  John S. Kresge

发明人： Frank D. Egitto ,  John S. Kresge

IPC分类号： B23K2618

CPC分类号： H05K3/0038 ,  B23K26/40 ,  B23K2101/34 ,  B23K2103/02 ,  B23K2103/05 ,  B23K2103/08 ,  B23K2103/10 ,  B23K2103/12 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L21/78 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/44 ,  H05K2201/09036 ,  H05K2201/0909

摘要： A method and associated structure for excising laminate chip carriers from a panel that has a thickness less than about 100 mils. A laser beam is focused on a surface of the panel, and the panel is moved relative to the laser beam in a geometric pattern, such that cells of the panel (e.g., chip carriers) are excised from the panel. The laser parameters include a wavelength between about 500 nanometers and about 600 nanometers, a pulse width greater than about 100 nanoseconds and less than about 350 nanoseconds, an average power of at least about 1 watt, a pulse repetition rate between about 5,000 pulses/sec and about 20,000 pulses/sec, and a target diameter (D) between about 2 microns and about 30 microns. The kerf width between adjacent excised cells is between about 2 microns and about 75 microns. The width of an excised cell is at least 5 mm. A displacement between successive pulses of the laser beam is less than about 2D. The panel may comprise a layered structure that includes an organic layer and a metal layer. The laser includes, inter alia, a lasant of Nd:YAG, Nd:YLF, Nd:YAP, or Nd:YVO4. The method of the present invention wastes less panel area by at least a factor of about 13 than does the mechanical excising techniques of the related art.

摘要翻译： 一种用于从厚度小于约100密耳的面板切割层压芯片载体的方法和相关结构。 激光束聚焦在面板的表面上，并且面板以几何图案相对于激光束移动，使得面板的单元（例如，芯片载体）从面板上被切除。 激光参数包括约500纳米至约600纳米之间的波长，大于约100纳秒且小于约350纳秒的脉冲宽度，至少约1瓦特的平均功率，约5,000脉冲/秒之间的脉冲重复率 和约20,000脉冲/秒，目标直径（D）在约2微米至约30微米之间。 相邻切割细胞之间的切口宽度在约2微米至约75微米之间。 切除的细胞的宽度至少为5mm。 激光束的连续脉冲之间的位移小于约2D。 面板可以包括层状结构，其包括有机层和金属层。 激光器尤其包括Nd：YAG，Nd：YLF，Nd：YAP或Nd：YVO4的农民。 与现有技术的机械切除技术相比，本发明的方法比面板面积少了约13倍。

公开(公告)号：US06351393B1

公开(公告)日：2002-02-26

申请号：US09346356

申请日：1999-07-02

申请人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K114

CPC分类号： H01L23/49822 ,  H01L23/3735 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

摘要翻译： 提供电子封装和制造电子封装的方法。 封装包括半导体芯片和多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 多层互连结构适于将半导体芯片与另外多个焊料连接的电路化基板（例如，电路板）电互连，并且包括由具有选定厚度和热系数的材料组成的导热层 从而基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 电子封装还包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。