公开(公告)号：US20140131857A1

公开(公告)日：2014-05-15

申请号：US13771524

申请日：2013-02-20

Applicant: QUALCOMM INCORPORATED

Inventor： Omar J. Bchir ,  Milind P. Shah ,  Houssam W. Jomaa ,  Manuel Aldrete ,  Chin-Kwan Kim

IPC: H01L23/498

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10175 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83192 ,  H05K1/092 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

公开(公告)号：US20240413137A1

公开(公告)日：2024-12-12

申请号：US18330435

申请日：2023-06-07

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Joan Rey Villarba Buot ,  Bohan Yan ,  Manuel Aldrete

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

Abstract: Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (“die”) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

公开(公告)号：US11804428B2

公开(公告)日：2023-10-31

申请号：US17097327

申请日：2020-11-13

Applicant: QUALCOMM Incorporated

Inventor： Wen Yin ,  Yonghao An ,  Manuel Aldrete

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49822

Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.

公开(公告)号：US10511268B2

公开(公告)日：2019-12-17

申请号：US15636626

申请日：2017-06-28

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Manuel Aldrete ,  Bonhoon Koo

IPC: H02H3/00 ,  H03F1/30 ,  H01L23/66 ,  H04B1/04

Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.

公开(公告)号：US10325859B1

公开(公告)日：2019-06-18

申请号：US15944233

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Manuel Aldrete

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/16

Abstract: Some features pertain to a stacked package apparatus that includes a shield at least partially surrounding the apparatus, a first substrate including a plurality of first pads, the plurality of first pads coupled to the shield, and a second substrate, the second substrate over the first substrate and coupled to the first substrate, the second substrate including a plurality of second pads, the plurality of second pads coupled to the shield.

公开(公告)号：US20170271266A1

公开(公告)日：2017-09-21

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US09768108B2

公开(公告)日：2017-09-19

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Milind Pravin Shah ,  Dwayne Richard Shirley

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

公开(公告)号：US20160148864A1

公开(公告)日：2016-05-26

申请号：US14703617

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  David Fraser Rae ,  Manuel Aldrete ,  Vladimir Noveski ,  Chin-Kwan Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L24/92 ,  H01L23/49811 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/152

Abstract: Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.

Abstract translation: 一些特征涉及集成电路器件，其包括第一封装衬底，耦合到第一封装衬底的第一管芯，第二封装衬底以及耦合到第一封装衬底和第二封装衬底的焊点结构。 焊接结构包括包含第一熔点温度的焊料和包含小于第一熔点温度的第二熔点温度的导电材料。 在一些实施方案中，导电材料是至少均质材料和/或异质材料之一。 在一些实施方案中，导电材料包括第一导电材料和第二材料。 导电材料是导电材料。

公开(公告)号：US09313881B2

公开(公告)日：2016-04-12

申请号：US13777298

申请日：2013-02-26

Applicant: Qualcomm Incorporated

Inventor： Christopher J. Healy ,  Gopal C. Jha ,  Manuel Aldrete

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H05K1/0271 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10145 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/3841 ,  H05K3/4038 ,  H05K2201/0305 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Improved Molded Laser Package (MLP) Packages which include a relief path for pressure and reduces the risk of shorting adjacent solder balls are provided. The MLP packages may include a gutter integrally connected to one or more through mold vias allowing a path to relieve pressure created when moisture gets entrapped in through mold vias, during the manufacturing process, while also reducing the risk of solder shorts between adjacent solder balls located in the through mold vias. Additionally, MLP packages which include gutters integrally connected to one or more through mold vias may enable tighter bump pitch and thinner packages. As a result, process margins and risks associated with surface mount technology (SMT) may be improved and provide more flexibility on inventory staging.

Abstract translation: 改进的模制激光封装（MLP）提供了包括压力释放路径和降低相邻焊球短路风险的封装。 MLP包装可以包括一个整体地连接到一个或多个通过模具通孔的沟槽，允许在制造过程期间通过模具通道将水分截留时产生的压力减小的路径，同时还降低相邻焊球之间的焊料短路的风险 在通孔中通孔。 此外，包括整体连接到一个或多个通过模具通孔的沟槽的MLP封装可以实现更紧密的突起间距和更薄的封装。 因此，可能会提高与表面贴装技术（SMT）相关的工艺余量和风险，并为库存阶段提供更大的灵活性。

公开(公告)号：US09269681B2

公开(公告)日：2016-02-23

申请号：US13741810

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Houssam W. Jomaa ,  Omar J. Bchir ,  Milind P. Shah ,  Manuel Aldrete ,  Chin-Kwan Kim

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/27011 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (μm) or less.

Abstract translation: 一些实施方案提供了一种半导体器件，其包括通过热压接工艺耦合到管芯的衬底。 半导体器件还包括耦合到衬底的迹线。 痕迹包括具有第一氧化性质的第一导电材料。 迹线还包括第一表面层，其包括具有第二氧化性质的第二导电材料。 第二氧化性比第一氧化性更不易氧化。 第一和第二导电材料被配置为在管芯和衬底之间提供电路径。 第一表面层的厚度为0.3微米（μm）以下。